Thanks for taking a close look at our bus timings. This may help explain whats happening and why it works:
1) On multiple writes, the "high width duration" is determined by nCE or nWE assertion as stated by note 1 on page 43 of the Intel C3 datasheet, document Order Number 290645-014 April 2002. On back-to-back writes, the minimum time is determined by the time between nCE assertions. The CPU can control the time between assertions by changing the value of ASET, RDAH, and WRAH for each chip select area. At reset, nCS0 starts with these values maxed out.
2) As stated above, this is ok per Intel specifications.

-Kurt

Thank you for the input.

I don't think the CPU can control the time between assertions of R/W#. For now, let's focus on the R/W# signal which is connected to the WE# of the boot flash. If you look at Fig. 17-23 and 17-25 of the MCF5475 ref. manual rev 2, adding AS and/or AH doesn't change the inactive time of R/W# during back-to-back writes. I think the problem here is that R/W# is outside of the active region CS#.

Correct. CPU cannot change when R/W# is controlled. The Intel data sheet states, the flash chip uses either the nCE or nWE signal (whichever is asserted the least amount) to determine the transactions. In this case nCE is the dominant signal and when it is deasserted, it ends the write cycle eventhough nWE = R/W# is still active beyond the nCE assertion.

I have copied the note from the Intel data sheet which explains the operation and why nCE is controlling this bus interface:

1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH.

Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.

Totally got it now. Thank you.

Now I have to find out if the AMD flash that I use work the same way. I will email AMD to find out.

AMD p/n Am29PDL128G also works similarly. The datasheet has a timing diagram for "Erase and Program Operations" and another timing diagram for "Alternate CE# Controlled Erase and Program Operations" at the end.