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Last Post 27 Jul 2016 04:11 PM by  bradb
GPMC bus vs. low-power operation
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YvesP
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Posts:2


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18 Jul 2016 08:10 AM

    A design note, on page 9 of the Torpedo Launcher 3 Baseboard Schematic (doc 1021666F) indicates that "Q7 and Q10 are an example of how to place the baseboard into a low power state however, due to the LAN and USB controllers, this feature cannot be used when the GPMC bus is active. Buffering the GPMC bus when in low power mode is recommended. Contact LogicPD support for reference designs".

    Is it possible to get a link to the above mentioned reference designs? Or are they only provided under service contract?

    Thanks.
    bradb
    Basic Member
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    Posts:203


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    19 Jul 2016 09:36 AM
    Due to problems with the USB and LAN controllers the current baseboard cannot be put in a low power mode. The USB and LAN controllers back feed the 1V8 power rail or resets the device when placing baseboard in low power mode.  Isolating the USB and LAN controller's as seen in the block diagram (TORPWL-18.pdf) will help resolve this issue.  
    YvesP
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    19 Jul 2016 04:39 PM
    Thanks Brad.

    A couple more questions if I may…

    Looking at the schematic, when the baseboard is placed in low power state, 1V8 and 3.3V are turned OFF by, respectively, Q10 and Q7. How do the USB and LAN controllers back feed the 1V8? What signal gets affected? When reset occurs, do both the SOM and controllers reset (as if SYS-nRESWARM got asserted?).

    In the suggested workaround, is it correct to say that while the address and data bus of the USB and LAN controllers are to be buffered by the SN74LVC32245 (and tri-stated based on up_nCS1 and up_nCS6), the control signals must be connected directly between the DM37x and the USB/LAN controller to allow proper operation outside of lower-power mode? … i.e. that up_nCS1 and up_nCS6 are to be connected to the nOE input of the SN74LVC32245 and to the chip select of the controllers, while up_nOE, up_nWE, SYS_NRESWARM, ALE, IRQ and FIFO_SEL signals are not to go through the buffer ?

    Has the workaround been implemented and shown to fix the issue?

    Thanks a lot.
    bradb
    Basic Member
    Basic Member
    Posts:203


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    27 Jul 2016 04:11 PM
    "Looking at the schematic, when the baseboard is placed in low power state, 1V8 and 3.3V are turned OFF by, respectively, Q10 and Q7. How do the USB and LAN controllers back feed the 1V8? What signal gets affected? When reset occurs, do both the SOM and controllers reset (as if SYS-nRESWARM got asserted?). "

    It is my understanding that when powering down the ISP1763 the reset line (ISP1763A.RESET_N, SYS_nRESWARM) is pulled low causing the SOM to reset.


    "In the suggested workaround, is it correct to say that while the address and data bus of the USB and LAN controllers are to be buffered by the SN74LVC32245 (and tri-stated based on up_nCS1 and up_nCS6), the control signals must be connected directly between the DM37x and the USB/LAN controller to allow proper operation outside of lower-power mode? … i.e. that up_nCS1 and up_nCS6 are to be connected to the nOE input of the SN74LVC32245 and to the chip select of the controllers, while up_nOE, up_nWE, SYS_NRESWARM, ALE, IRQ and FIFO_SEL signals are not to go through the buffer ? "

    The understanding is that all signals between the USB/LAN signals must be buffered. I will verify this with our developer.

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