Fred,

The really short answer is to read the i.MX31 Reference Manual.

The significantly longer answer goes something like this:

The MX31 register configuration is pretty complicated, and is in a sense multi-level. The bottom level is the SW_MUX_CTL registers, which each contain fields for every signal pin on the MX31. Each register controls 4 pins independantly. For example, if you see on page 4-9 of the MX31RM, you can see how each register controls the input and output muxing for each pin. The SW_MUX_OUT_EN field controls which output is applied to an output pin, while the other four fields control where the input signal is routed internally.

Above the SW_MUX_CTL registers is the General Purpose Register (Section 4.3.2 of the MX31RM). The bits in this register control the functionality for large groups of signals, overriding the programming in the SW_MUX_CTL register. Within the GPR itself, there are two sets of signals, Hardware Mode 1 and Hardware Mode 2, with HW2 having priority over HW1.

All of this is captured in Table 4-8, which lists the HW1 and HW2 modes next to the SW_MUX_CTL modes.

Why do this? Basically, the GPR allows signal groups to be quickly changed from one configuration to another, without having to reload every register associated with the configuration. This is usually for situations where signal groups can be part-time as one or another set of signals. The classic example of this is the interface plug on the bottom of older phones. When these phones first came out, almost all PCs had serial ports, but few had USB ports. So it made sense to multiplex the USB and serial port signals on the same pins. With the GPR register, you could quickly change from using a serial interface to a USB interface.

As an example, let's say we have an ATA port on a device that is only used part-time, so we mux it with the camera. The SW_MUX_CTL signals for the shared pins would be configured for the IPU CSI. When an ATA device is inserted, GPR[6] is set to 1, allowing the ATA signals to override the IPU CSI. When the ATA device is removed, GPR[6] can be
cleared to allow the IPU CSI access to the shared pins again.

For a concrete example, to configure PC_BVD1 and PC_BVD2 for UART5 RXD and TXD, look at page 4-55. The SW_MUX_CTL setting for both is Alternate Mode 2. There are no hardware mode ramifications for these
two signals, so the GPR can be ignored.

PC_BVD1 -> UART5_RXD -> alternate mode 2 (input)
sw_mux_ctl_pc_bvd1 = 0b000 1000
PC_BVD2 -> UART5_TXD -> alternate mode 2 (output)
sw_mux_ctl_pc_bvd2 = 0b011 0000

Notice that on page 4-25, the register that holds sw_mux_ctl_pc_bvd1 has reserved bits for bit 8, because pc_bvd1 doesn't have a GPIO port associated with it (see page 4-55). sw_mux_ctl_pc_bvd2 has reserved bits for bit 0 and bit 3, because pc_bvd2 doesn't have a GPIO port either and mode 2 for that port is output only, so there is no option for an input alternate mode 2.

For another example, let's configure RI_DTE1 as a GPIO (page 4-63). It does have a hardware mode in the GPR register, so first we have to make sure GPR[2] is cleared. Then, sw_mux_ctl_pc_ri_dte1 must be set to 0b000 0001. This configures the input and outputs to the GPIO port.

If you need more specific help with setting up the GPIO on our Kits, the applications engineering team is available through our support contract system to work with you on your specific needs.

Thanks