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Last Post 04 Feb 2013 12:32 PM by dtran11

U-Boot 2012.07 \w SPL, Linux 3.2, Boot from SD card or NAND

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dtran11

New Member
Posts:23

26 Sep 2012 04:45 PM
Just wanted to let the group know that you can replace LogicLoader with UBoot completely if you like. I was able to do this with some patches. Let me know if anyone wants them.

MarcoPhx

New Member
Posts:

04 Oct 2012 02:24 AM
Just for curiosity, what kind of advantages do you have with u-boot, compared to Lolo ? Regards

dtran11

New Member
Posts:23

09 Oct 2012 11:24 AM
I don't know if Lolo is opensource or not but u-boot definitely is. Also u-boot is really fast now. U-boot takes less than 2 seconds to load my kernel. My total system bootup time is down to 5 seconds now.

tamotsu

New Member
Posts:3

02 Jan 2013 03:19 PM
Posted By dtran11 on 26 Sep 2012 4:45 PM Just wanted to let the group know that you can replace LogicLoader with UBoot completely if you like. I was able to do this with some patches. Let me know if anyone wants them. I am interested in. Can you make the patches available? Can you build fw_setenv tool as well? Thanks, --tamotsu

dtran11

New Member
Posts:23

15 Jan 2013 04:05 PM
Posted By tamotsu on 2 Jan 2013 3:19 PM I am interested in. Can you make the patches available? Can you build fw_setenv tool as well? Thanks, --tamotsu Sorry I haven't been active with this forum. I'll try to put something together for you in the next week.

dtran11

New Member
Posts:23

04 Feb 2013 12:28 PM
Here are my patches for u-boot 2012.07 diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -34,10 +34,6 @@ #define CONFIG_OMAP34XX /* which is a 34XX / #define CONFIG_OMAP3_LOGIC / working with Logic OMAP boards / -#undef CONFIG_USE_IRQ / no support for IRQs / - -#define CONFIG_SYS_TEXT_BASE 0x80400000 - #define CONFIG_SDRC / The chip has SDRC controller / #include <asm/arch/cpu.h> / get chip and board defs / @@ -53,14 +49,16 @@ #define V_OSCK 26000000 / Clock output from T2 / #define V_SCLK (V_OSCK >> 1) -#define CONFIG_MISC_INIT_R / misc_init_r dumps the die id / +#undef CONFIG_USE_IRQ / no support for IRQs / +#define CONFIG_MISC_INIT_R +#define CONFIG_BOARD_LATE_INIT #define CONFIG_CMDLINE_TAG / enable passing of ATAGs / #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG -#define CONFIG_CMDLINE_EDITING / cmd line edit/history / +#define CONFIG_OF_LIBFDT #define CONFIG_ZERO_BOOTDELAY_CHECK / check keypress w/no delay / / @@ -108,40 +106,25 @@ #define CONFIG_CMD_EXT2 /* EXT2 Support / #define CONFIG_CMD_FAT / FAT support / #define CONFIG_CMD_JFFS2 / JFFS2 Support / -#define CONFIG_CMD_MTDPARTS / Enable MTD parts commands / -#define CONFIG_MTD_DEVICE / needed for mtdparts commands / -#define MTDIDS_DEFAULT "nand0=omap2-nand.0" -#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(x-loader),"\ - "1920k(u-boot),128k(u-boot-env),"\ - "4m(kernel),-(fs)" #define CONFIG_CMD_I2C / I2C serial bus support / #define CONFIG_CMD_MMC / MMC support / #define CONFIG_CMD_NAND / NAND support / -#define CONFIG_CMD_NAND_LOCK_UNLOCK / nand (un)lock commands / -#define CONFIG_CMD_NET / bootp, tftpboot, rarpboot / -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_SETEXPR / Evaluate expressions / +#define CONFIG_CMD_NAND_LOCK_UNLOCK #undef CONFIG_CMD_FLASH / flinfo, erase, protect / #undef CONFIG_CMD_FPGA / FPGA configuration Support / #undef CONFIG_CMD_IMI / iminfo / #undef CONFIG_CMD_IMLS / List all found images / +#undef CONFIG_CMD_NFS / NFS support / +#define CONFIG_CMD_NET / bootp, tftpboot, rarpboot / #define CONFIG_SYS_NO_FLASH - -/ - * I2C - / #define CONFIG_HARD_I2C -#define CONFIG_DRIVER_OMAP34XX_I2C - #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_BUS 0 -#define CONFIG_SYS_I2C_BUS_SELECT 1 #define CONFIG_I2C_MULTI_BUS +#define CONFIG_DRIVER_OMAP34XX_I2C / * TWL4030 @@ -156,11 +139,12 @@ #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address / / to access nand / #define CONFIG_SYS_NAND_BASE NAND_BASE / physical address / - / to access nand at / - / CS0 / + / to access nand / + / at CS0 / +#define GPMC_NAND_ECC_LP_x16_LAYOUT -#define CONFIG_SYS_MAX_NAND_DEVICE 1 / Max number of / - / NAND devices / +#define CONFIG_SYS_MAX_NAND_DEVICE 1 / Max number of NAND / + / devices / #define CONFIG_JFFS2_NAND / nand device jffs2 lives on / #define CONFIG_JFFS2_DEV "nand0" @@ -170,91 +154,62 @@ / partition / / Environment information / -#define CONFIG_BOOTDELAY 2 - -/ - * PREBOOT assumes the 4.3" display is attached. User can interrupt - * and modify display variable to suit their needs. - / -#define CONFIG_PREBOOT \ - "echo ======================NOTICE============================;"\ - "echo \"The u-boot environment is not set.\";" \ - "echo \"If using a display a valid display varible for your panel\";" \ - "echo \"needs to be set.\";" \ - "echo \"Valid display options are:\";" \ - "echo \" 2 == LQ121S1DG31 TFT SVGA (12.1) Sharp\";" \ - "echo \" 3 == LQ036Q1DA01 TFT QVGA (3.6) Sharp w/ASIC\";" \ - "echo \" 5 == LQ064D343 TFT VGA (6.4) Sharp\";" \ - "echo \" 7 == LQ10D368 TFT VGA (10.4) Sharp\";" \ - "echo \" 15 == LQ043T1DG01 TFT WQVGA (4.3) Sharp (DEFAULT)\";" \ - "echo \" vga[-dvi or -hdmi] LCD VGA 640x480\";" \ - "echo \" svga[-dvi or -hdmi] LCD SVGA 800x600\";" \ - "echo \" xga[-dvi or -hdmi] LCD XGA 1024x768\";" \ - "echo \" 720p[-dvi or -hdmi] LCD 720P 1280x720\";" \ - "echo \"Defaulting to 4.3 LCD panel (display=15).\";" \ - "setenv display 15;" \ - "setenv preboot;" \ - "saveenv;" - +#define CONFIG_BOOTDELAY 5 #define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x81000000\0" \ - "bootfile=uImage\0" \ - "mtdids=" MTDIDS_DEFAULT "\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "loadaddr=0x82000000\0" \ + "console=ttyO0,115200n8\0" \ + "mpurate=500\0" \ + "optargs=\0" \ + "vram=12M\0" \ + "dvimode=1024x768MR-16@60\0" \ + "defaultdisplay=dvi\0" \ "mmcdev=0\0" \ - "autoboot=if mmc rescan ${mmcdev}; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "run defaultboot;" \ - "fi; " \ - "else run defaultboot; fi\0" \ - "defaultboot=run mmcramboot\0" \ - "consoledevice=ttyO0\0" \ - "display=15\0" \ - "setconsole=setenv console ${consoledevice},${baudrate}n8\0" \ - "dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \ - "rotation=0\0" \ - "vrfb_arg=if itest ${rotation} -ne 0; then " \ - "setenv bootargs ${bootargs} omapfb.vrfb=y " \ - "omapfb.rotate=${rotation}; " \ - "fi\0" \ - "otherbootargs=ignore_loglevel early_printk no_console_suspend\0" \ - "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "common_bootargs=setenv bootargs ${bootargs} display=${display} " \ - "${otherbootargs};" \ - "run addmtdparts; " \ - "run vrfb_arg\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "nandroot=ubi0:rootfs ubi.mtd=4\0" \ + "nandrootfstype=ubifs\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "mpurate=${mpurate} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "mpurate=${mpurate} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo 'Running bootscript from mmc ...'; " \ + "bootscript=echo Running bootscript from mmc ...; " \ "source ${loadaddr}\0" \ - "loaduimage=mmc rescan ${mmcdev}; " \ - "fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ - "ramdisksize=64000\0" \ - "ramdiskaddr=0x82000000\0" \ - "ramdiskimage=rootfs.ext2.gz.uboot\0" \ - "ramargs=run setconsole; setenv bootargs console=${console} " \ - "root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \ - "mmcramboot=echo 'Booting kernel from mmc w/ramdisk...'; " \ - "run ramargs; " \ - "run common_bootargs; " \ - "run dump_bootargs; " \ - "run loaduimage; " \ - "fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}; "\ - "bootm ${loadaddr} ${ramdiskaddr}\0" \ - "ramboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \ - "run ramargs; " \ - "run common_bootargs; " \ - "run dump_bootargs; " \ - "tftpboot ${loadaddr} ${bootfile}; "\ - "tftpboot ${ramdiskaddr} ${ramdiskimage}; "\ - "bootm ${loadaddr} ${ramdiskaddr}\0" + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "run autoboot" + "if mmc rescan ${mmcdev}; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" -#define CONFIG_AUTO_COMPLETE +#define CONFIG_AUTO_COMPLETE 1 / * Miscellaneous configurable options / @@ -265,9 +220,10 @@ / Print Buffer Size / #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 / max number of command args / +#define CONFIG_SYS_MAXARGS 16 / max number of command / + / args / / Boot Argument Buffer Size / -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE / memtest works on / #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ @@ -275,31 +231,30 @@ #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) / default load / / address / - / * OMAP3 has 12 GP timers, they can be driven by the system clock * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). * This rate is divided by a local divisor. / -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 #define CONFIG_SYS_PTV 2 / Divisor: 2^(PTV+1) => 8 / #define CONFIG_SYS_HZ 1000 -/ +/----------------------------------------------------------------------- Stack sizes * * The stack sizes are set up in start.S using the settings below / #define CONFIG_STACKSIZE (128 << 10) / regular stack 128 KiB / -/ +/----------------------------------------------------------------------- Physical Memory Map / #define CONFIG_NR_DRAM_BANKS 2 / CS1 may or may not be populated / #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 -/ +/----------------------------------------------------------------------- FLASH and environment organization / @@ -307,55 +262,206 @@ / Configure the PISMO / #define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M #define CONFIG_SYS_MONITOR_LEN (256 << 10) / Reserve 2 sectors / #if defined(CONFIG_CMD_NAND) #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE -#elif defined(CONFIG_CMD_ONENAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE #endif / Monitor at start of flash / #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP -#define SMNAND_ENV_OFFSET 0x260000 / environment starts here / - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET -#endif +#define ONENAND_ENV_OFFSET 0x240000 / environment starts here / +#define SMNAND_ENV_OFFSET 0x240000 / environment starts here / #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) / 128 KiB / -#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET -/ - * SMSC922x Ethernet - / #if defined(CONFIG_CMD_NET) +/---------------------------------------------------------------------------- + * SMSC9211 Ethernet from SMSC9118 family + ---------------------------------------------------------------------------- + / #define CONFIG_SMC911X -#define CONFIG_SMC911X_16_BIT -#define CONFIG_SMC911X_BASE 0x08000000 +#define CONFIG_SMC911X_32_BIT +#define CONFIG_SMC911X_BASE 0x2C000000 #endif /* (CONFIG_CMD_NET) / / - * BOOTP fields + * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader + * and older u-boot.bin with the new U-Boot SPL. / +#define CONFIG_SYS_TEXT_BASE 0x80008000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/ Defines for SPL / +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (54 1024) /* 8 KB for stack / +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +/ move malloc and bss high to prevent clashing with the main image / +#define CONFIG_SYS_SPL_MALLOC_START 0x87000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 +#define CONFIG_SPL_BSS_START_ADDR 0x87080000 / end of minimum RAM / +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 / 512 KB / + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 / address 0x60000 / +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 / 256 KB / +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/ NAND boot config / +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (1281024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + + +/#define CONFIG_FAST_BOOT/ +/#define CONFIG_FAST_BOOT_MMC/ +/#define CONFIG_FAST_BOOT_NAND/ + +#ifdef CONFIG_FAST_BOOT + + #define CONFIG_SILENT_CONSOLE 1 + #define CONFIG_ENV_IS_NOWHERE 1 + #undef CONFIG_ENV_IS_IN_NAND + + #undef CONFIG_SYS_LONGHELP + #undef CONFIG_AUTO_COMPLETE + #undef CONFIG_SYS_HUSH_PARSER + #undef CONFIG_REVISION_TAG + #undef CONFIG_MD5 + #undef CONFIG_SHA1 + #undef CONFIG_BZIP2 + #undef CONFIG_LZMA + + #undef CONFIG_CMD_BDI + #undef CONFIG_CMD_BOOTD + #undef CONFIG_CMD_CONSOLE + #undef CONFIG_CMD_ECHO + #undef CONFIG_CMD_EDITENV + #undef CONFIG_CMD_FPGA + #undef CONFIG_CMD_FLASH + #undef CONFIG_CMD_IMI + #undef CONFIG_CMD_IMLS + #undef CONFIG_CMD_ITEST + #undef CONFIG_CMD_LOADB + #undef CONFIG_CMD_LOADS + #undef CONFIG_CMD_MEMORY + #undef CONFIG_CMD_MISC +/* #undef CONFIG_CMD_NET -- Doesn't work for some reason. Give some linker errors / + #undef CONFIG_CMD_NFS + #undef CONFIG_CMD_SETGETDCR + #undef CONFIG_CMD_SOURCE + #undef CONFIG_CMD_XIMG + + #undef CONFIG_CMD_EXT2 + #undef CONFIG_CMD_JFFS2 + #undef CONFIG_CMD_USB + #undef CONFIG_NET_MULTI + #undef CONFIG_SMC911X + #undef CONFIG_OF_LIBFDT + #undef CONFIG_FIT + + #undef CONFIG_EXTRA_ENV_SETTINGS + #define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=no\0" \ + "bootfile=uImage\0" + + #undef CONFIG_BOOTDELAY + #define CONFIG_BOOTDELAY 0 + + #ifdef CONFIG_FAST_BOOT_MMC + #undef CONFIG_SYS_NAND_QUIET_TEST + #undef CONFIG_NAND_OMAP_GPMC + #undef CONFIG_CMD_NAND + #undef CONFIG_SPL_NAND_SUPPORT + #undef CONFIG_CMD_NAND_LOCK_UNLOCK + + #undef CONFIG_BOOTCOMMAND + #define CONFIG_BOOTCOMMAND \ + "mmc rescan 0; " \ + "fatload mmc 0 0x82000000 uImage; " \ + "bootm 0x82000000;" + + #undef CONFIG_BOOTARGS + #define CONFIG_BOOTARGS \ + "console=ttyO0,115200n8 " \ + "mpurate=600 " \ + "quiet noinitrd " \ + "root=/dev/mmcblk0p2 rw " \ + "rootfstype=ext3 rootwait " + #else + #undef CONFIG_OMAP3_MMC + #undef CONFIG_CMD_MMC + /#undef CONFIG_CMD_FAT/ + / #undef CONFIG_DOS_PARTITION / + + #undef CONFIG_BOOTCOMMAND + #define CONFIG_BOOTCOMMAND \ + "nand read 0x82000000 280000 400000; " \ + "bootm 0x82000000;" + + #undef CONFIG_BOOTARGS + #define CONFIG_BOOTARGS \ + "console=ttyO0,115200n8 " \ + "mpurate=600 " \ + "quiet noinitrd " \ + "root=ubi0:rootfs ubi.mtd=4 " \ + "rootfstype=ubifs " + #endif / #ifdef CONFIG_FAST_BOOT_MMC / + + + #undef CONFIG_USB_OMAP3 + #undef CONFIG_MUSB_HCD + + #undef CONFIG_USB_STORAGE + #undef CONFIG_USB_KEYBOARD + #undef CONFIG_SYS_USB_EVENT_POLL + #undef CONFIG_PREBOOT + + #undef CONFIG_MUSB_UDC + #undef CONFIG_USB_DEVICE + #undef CONFIG_USB_TTY + +#endif / CONFIG_FAST_BOOT / -#define CONFIG_BOOTP_SUBNETMASK 0x00000001 -#define CONFIG_BOOTP_GATEWAY 0x00000002 -#define CONFIG_BOOTP_HOSTNAME 0x00000004 -#define CONFIG_BOOTP_BOOTPATH 0x00000010 #endif / __CONFIG_H / diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -137,6 +137,54 @@ int board_init(void) return 0; } +/ + * Routine: omap_rev_string + * Description: For SPL builds output board rev + / +#ifdef CONFIG_SPL_BUILD +void omap_rev_string(void) +{ +} +#endif + +#ifdef CONFIG_SPL_BUILD +/ + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + / +void get_board_mem_timings(u32 mcfg, u32 ctrla, u32 ctrlb, u32 rfr_ctrl, + u32 mr) +{ + mr = MICRON_V_MR_165; + switch (0) { + case 0: / Micron 1286MB/256MB, 1/2 banks of 128MB / + mcfg = MICRON_V_MCFG_165(128 << 20); + ctrla = MICRON_V_ACTIMA_165; + ctrlb = MICRON_V_ACTIMB_165; + rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + break; + case 1: / Micron 256MB/512MB, 1/2 banks of 256MB / + mcfg = MICRON_V_MCFG_165(256 << 20); + ctrla = MICRON_V_ACTIMA_165; + ctrlb = MICRON_V_ACTIMB_165; + rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + break; + case 2: / Hynix 256MB/512MB, 1/2 banks of 256MB / + mcfg = HYNIX_V_MCFG_165(256 << 20); + ctrla = HYNIX_V_ACTIMA_165; + ctrlb = HYNIX_V_ACTIMB_165; + rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + break; + default: + mcfg = MICRON_V_MCFG_165(128 << 20); + ctrla = MICRON_V_ACTIMA_165; + ctrlb = MICRON_V_ACTIMB_165; + rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } +} +#endif + #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t bis) { @@ -164,16 +212,21 @@ int board_eth_init(bd_t bis) } #endif +#ifdef CONFIG_BOARD_LATE_INIT / - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin + * Routine: late_board_init + * Description: Late hardware init. / +int board_late_init(void) +{ + #ifdef CONFIG_CMD_NAND_LOCK_UNLOCK + // Unlock the whole chip + nand_unlock(&nand_info[0], 0x0, nand_info[0].size); + #endif + + return 0; +} +#endif / * Routine: set_muxconf_regs @@ -183,69 +236,5 @@ int board_eth_init(bd_t bis) / void set_muxconf_regs(void) { - /GPMC/ - MUX_VAL(CP(GPMC_A1), (IDIS \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_A2), (IDIS \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_A3), (IDIS \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_A4), (IDIS \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_A5), (IDIS \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_A6), (IDIS \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_A7), (IDIS \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_A8), (IDIS \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_A9), (IDIS \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_A10), (IDIS \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_D0), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_D1), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_D2), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_D3), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_D4), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_D5), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_D6), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_D7), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_D8), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_D9), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_D10), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_D11), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_D12), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_D13), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_D14), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_D15), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_NCS0), (IDIS \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_NCS1), (IDIS \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_NCS2), (IDIS \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_NCS3), (IDIS \| PTD \| DIS \| M0)); - MUX_VAL(CP(GPMC_NCS5), (IDIS \| PTU \| DIS \| M4)); - MUX_VAL(CP(GPMC_NCS7), (IDIS \| PTD \| DIS \| M1)); /GPMC_IO_DIR/ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS \| PTU \| EN \| M0)); - MUX_VAL(CP(GPMC_WAIT1), (IEN \| PTU \| EN \| M0)); - - /Expansion card / - MUX_VAL(CP(MMC1_CLK), (IDIS \| PTU \| EN \| M0)); - MUX_VAL(CP(MMC1_CMD), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(MMC1_DAT0), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(MMC1_DAT1), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(MMC1_DAT2), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(MMC1_DAT3), (IEN \| PTU \| EN \| M0)); - - /* Serial Console / - MUX_VAL(CP(UART1_TX), (IDIS \| PTD \| DIS \| M0)); - MUX_VAL(CP(UART1_RTS), (IDIS \| PTD \| DIS \| M0)); - MUX_VAL(CP(UART1_CTS), (IEN \| PTU \| DIS \| M0)); - MUX_VAL(CP(UART1_RX), (IEN \| PTD \| DIS \| M0)); - - / I2C / - MUX_VAL(CP(I2C2_SCL), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(I2C2_SDA), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(I2C3_SCL), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(I2C3_SDA), (IEN \| PTU \| EN \| M0)); - - MUX_VAL(CP(HDQ_SIO), (IEN \| PTU \| EN \| M0)); - - /Control and debug / - MUX_VAL(CP(SYS_NIRQ), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(SYS_OFF_MODE), (IEN \| PTD \| DIS \| M0)); - MUX_VAL(CP(SYS_CLKOUT1), (IEN \| PTD \| DIS \| M0)); - MUX_VAL(CP(SYS_CLKOUT2), (IEN \| PTU \| EN \| M0)); - MUX_VAL(CP(JTAG_nTRST), (IEN \| PTD \| DIS \| M0)); - MUX_VAL(CP(SDRC_CKE0), (IDIS \| PTU \| EN \| M0)); + MUX_OMAP3LOGIC(); } diff --git a/board/logicpd/omap3som/omap3logic.h b/board/logicpd/omap3som/omap3logic.h --- a/board/logicpd/omap3som/omap3logic.h +++ b/board/logicpd/omap3som/omap3logic.h @@ -38,10 +38,264 @@ const omap3_sysinfo sysinfo = { - DDR_DISCRETE, + DDR_STACKED, "Logic DM37x/OMAP35x reference board", "NAND", }; +/ + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + / +#define MUX_OMAP3LOGIC() \ + /SDRC/\ + MUX_VAL(CP(SDRC_D0), (IEN \| PTD \| DIS \| M0)) /SDRC_D0/\ + MUX_VAL(CP(SDRC_D1), (IEN \| PTD \| DIS \| M0)) /SDRC_D1/\ + MUX_VAL(CP(SDRC_D2), (IEN \| PTD \| DIS \| M0)) /SDRC_D2/\ + MUX_VAL(CP(SDRC_D3), (IEN \| PTD \| DIS \| M0)) /SDRC_D3/\ + MUX_VAL(CP(SDRC_D4), (IEN \| PTD \| DIS \| M0)) /SDRC_D4/\ + MUX_VAL(CP(SDRC_D5), (IEN \| PTD \| DIS \| M0)) /SDRC_D5/\ + MUX_VAL(CP(SDRC_D6), (IEN \| PTD \| DIS \| M0)) /SDRC_D6/\ + MUX_VAL(CP(SDRC_D7), (IEN \| PTD \| DIS \| M0)) /SDRC_D7/\ + MUX_VAL(CP(SDRC_D8), (IEN \| PTD \| DIS \| M0)) /SDRC_D8/\ + MUX_VAL(CP(SDRC_D9), (IEN \| PTD \| DIS \| M0)) /SDRC_D9/\ + MUX_VAL(CP(SDRC_D10), (IEN \| PTD \| DIS \| M0)) /SDRC_D10/\ + MUX_VAL(CP(SDRC_D11), (IEN \| PTD \| DIS \| M0)) /SDRC_D11/\ + MUX_VAL(CP(SDRC_D12), (IEN \| PTD \| DIS \| M0)) /SDRC_D12/\ + MUX_VAL(CP(SDRC_D13), (IEN \| PTD \| DIS \| M0)) /SDRC_D13/\ + MUX_VAL(CP(SDRC_D14), (IEN \| PTD \| DIS \| M0)) /SDRC_D14/\ + MUX_VAL(CP(SDRC_D15), (IEN \| PTD \| DIS \| M0)) /SDRC_D15/\ + MUX_VAL(CP(SDRC_D16), (IEN \| PTD \| DIS \| M0)) /SDRC_D16/\ + MUX_VAL(CP(SDRC_D17), (IEN \| PTD \| DIS \| M0)) /SDRC_D17/\ + MUX_VAL(CP(SDRC_D18), (IEN \| PTD \| DIS \| M0)) /SDRC_D18/\ + MUX_VAL(CP(SDRC_D19), (IEN \| PTD \| DIS \| M0)) /SDRC_D19/\ + MUX_VAL(CP(SDRC_D20), (IEN \| PTD \| DIS \| M0)) /SDRC_D20/\ + MUX_VAL(CP(SDRC_D21), (IEN \| PTD \| DIS \| M0)) /SDRC_D21/\ + MUX_VAL(CP(SDRC_D22), (IEN \| PTD \| DIS \| M0)) /SDRC_D22/\ + MUX_VAL(CP(SDRC_D23), (IEN \| PTD \| DIS \| M0)) /SDRC_D23/\ + MUX_VAL(CP(SDRC_D24), (IEN \| PTD \| DIS \| M0)) /SDRC_D24/\ + MUX_VAL(CP(SDRC_D25), (IEN \| PTD \| DIS \| M0)) /SDRC_D25/\ + MUX_VAL(CP(SDRC_D26), (IEN \| PTD \| DIS \| M0)) /SDRC_D26/\ + MUX_VAL(CP(SDRC_D27), (IEN \| PTD \| DIS \| M0)) /SDRC_D27/\ + MUX_VAL(CP(SDRC_D28), (IEN \| PTD \| DIS \| M0)) /SDRC_D28/\ + MUX_VAL(CP(SDRC_D29), (IEN \| PTD \| DIS \| M0)) /SDRC_D29/\ + MUX_VAL(CP(SDRC_D30), (IEN \| PTD \| DIS \| M0)) /SDRC_D30/\ + MUX_VAL(CP(SDRC_D31), (IEN \| PTD \| DIS \| M0)) /SDRC_D31/\ + MUX_VAL(CP(SDRC_CLK), (IEN \| PTD \| DIS \| M0)) /SDRC_CLK/\ + MUX_VAL(CP(SDRC_DQS0), (IEN \| PTD \| DIS \| M0)) /SDRC_DQS0/\ + MUX_VAL(CP(SDRC_DQS1), (IEN \| PTD \| DIS \| M0)) /SDRC_DQS1/\ + MUX_VAL(CP(SDRC_DQS2), (IEN \| PTD \| DIS \| M0)) /SDRC_DQS2/\ + MUX_VAL(CP(SDRC_DQS3), (IEN \| PTD \| DIS \| M0)) /SDRC_DQS3/\ + /GPMC/\ + MUX_VAL(CP(GPMC_A1), (IDIS \| PTU \| EN \| M0)) /GPMC_A1/\ + MUX_VAL(CP(GPMC_A2), (IDIS \| PTU \| EN \| M0)) /GPMC_A2/\ + MUX_VAL(CP(GPMC_A3), (IDIS \| PTU \| EN \| M0)) /GPMC_A3/\ + MUX_VAL(CP(GPMC_A4), (IDIS \| PTU \| EN \| M0)) /GPMC_A4/\ + MUX_VAL(CP(GPMC_A5), (IDIS \| PTU \| EN \| M0)) /GPMC_A5/\ + MUX_VAL(CP(GPMC_A6), (IDIS \| PTU \| EN \| M0)) /GPMC_A6/\ + MUX_VAL(CP(GPMC_A7), (IDIS \| PTU \| EN \| M0)) /GPMC_A7/\ + MUX_VAL(CP(GPMC_A8), (IDIS \| PTU \| EN \| M0)) /GPMC_A8/\ + MUX_VAL(CP(GPMC_A9), (IDIS \| PTU \| EN \| M0)) /GPMC_A9/\ + MUX_VAL(CP(GPMC_A10), (IDIS \| PTU \| EN \| M0)) /GPMC_A10/\ + MUX_VAL(CP(GPMC_D0), (IEN \| PTU \| EN \| M0)) /GPMC_D0/\ + MUX_VAL(CP(GPMC_D1), (IEN \| PTU \| EN \| M0)) /GPMC_D1/\ + MUX_VAL(CP(GPMC_D2), (IEN \| PTU \| EN \| M0)) /GPMC_D2/\ + MUX_VAL(CP(GPMC_D3), (IEN \| PTU \| EN \| M0)) /GPMC_D3/\ + MUX_VAL(CP(GPMC_D4), (IEN \| PTU \| EN \| M0)) /GPMC_D4/\ + MUX_VAL(CP(GPMC_D5), (IEN \| PTU \| EN \| M0)) /GPMC_D5/\ + MUX_VAL(CP(GPMC_D6), (IEN \| PTU \| EN \| M0)) /GPMC_D6/\ + MUX_VAL(CP(GPMC_D7), (IEN \| PTU \| EN \| M0)) /GPMC_D7/\ + MUX_VAL(CP(GPMC_D8), (IEN \| PTU \| EN \| M0)) /GPMC_D8/\ + MUX_VAL(CP(GPMC_D9), (IEN \| PTU \| EN \| M0)) /GPMC_D9/\ + MUX_VAL(CP(GPMC_D10), (IEN \| PTU \| EN \| M0)) /GPMC_D10/\ + MUX_VAL(CP(GPMC_D11), (IEN \| PTU \| EN \| M0)) /GPMC_D11/\ + MUX_VAL(CP(GPMC_D12), (IEN \| PTU \| EN \| M0)) /GPMC_D12/\ + MUX_VAL(CP(GPMC_D13), (IEN \| PTU \| EN \| M0)) /GPMC_D13/\ + MUX_VAL(CP(GPMC_D14), (IEN \| PTU \| EN \| M0)) /GPMC_D14/\ + MUX_VAL(CP(GPMC_D15), (IEN \| PTU \| EN \| M0)) /GPMC_D15/\ + MUX_VAL(CP(GPMC_NCS0), (IDIS \| PTU \| EN \| M0)) /GPMC_nCS0/\ + MUX_VAL(CP(GPMC_NCS1), (IDIS \| PTU \| EN \| M0)) /GPMC_nCS1/\ + MUX_VAL(CP(GPMC_NCS2), (IDIS \| PTU \| EN \| M0)) /GPMC_nCS2/\ + MUX_VAL(CP(GPMC_NCS3), (IDIS \| PTU \| EN \| M0)) /GPMC_nCS3(CF)/\ + MUX_VAL(CP(GPMC_NCS4), (IDIS \| PTU \| EN \| M0)) /GPMC_nCS4(ext.A)/\ + MUX_VAL(CP(GPMC_NCS5), (IDIS \| PTU \| EN \| M0)) /GPMC_nCS5(ext.B)/\ + MUX_VAL(CP(GPMC_NCS6), (IDIS \| PTU \| EN \| M0)) /GPMC_nCS6(USB)/\ + MUX_VAL(CP(GPMC_NCS7), (IEN \| PTU \| EN \| M1)) /GPMC_IO_DIR(ext.)/\ + MUX_VAL(CP(GPMC_NBE1), (IDIS \| PTU \| EN \| M0)) /GPMC_nBE1(ext.)/\ + MUX_VAL(CP(GPMC_CLK), (IEN \| PTD \| DIS \| M0)) /GPMC_CLK/\ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS \| PTD \| DIS \| M0)) /GPMC_nADV_ALE/\ + MUX_VAL(CP(GPMC_NOE), (IDIS \| PTD \| DIS \| M0)) /GPMC_nOE/\ + MUX_VAL(CP(GPMC_NWE), (IDIS \| PTD \| DIS \| M0)) /GPMC_nWE/\ + MUX_VAL(CP(GPMC_NBE0_CLE), (IEN \| PTU \| EN \| M0)) /GPMC_nBE0_CLE/\ + MUX_VAL(CP(GPMC_NWP), (IEN \| PTU \| EN \| M0)) /GPMC_nWP/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN \| PTU \| EN \| M0)) /GPMC_WAIT0/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN \| PTU \| EN \| M0)) /GPMC_WAIT1/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN \| PTU \| EN \| M0)) /GPMC_WAIT2/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN \| PTU \| EN \| M1)) /uP_DREQ1(ext.)/\ + /Expansion card /\ + MUX_VAL(CP(MMC1_CLK), (IEN \| PTU \| EN \| M0)) /MMC1_CLK/\ + MUX_VAL(CP(MMC1_CMD), (IEN \| PTU \| EN \| M0)) /MMC1_CMD/\ + MUX_VAL(CP(MMC1_DAT0), (IEN \| PTU \| EN \| M0)) /MMC1_DAT0/\ + MUX_VAL(CP(MMC1_DAT1), (IEN \| PTU \| EN \| M0)) /MMC1_DAT1/\ + MUX_VAL(CP(MMC1_DAT2), (IEN \| PTU \| EN \| M0)) /MMC1_DAT2/\ + MUX_VAL(CP(MMC1_DAT3), (IEN \| PTU \| EN \| M0)) /MMC1_DAT3/\ + MUX_VAL(CP(MMC1_DAT4), (IEN \| PTU \| EN \| M0)) /MMC1_DAT4/\ + MUX_VAL(CP(MMC1_DAT5), (IEN \| PTU \| EN \| M0)) /MMC1_DAT5/\ + MUX_VAL(CP(MMC1_DAT6), (IEN \| PTU \| EN \| M0)) /MMC1_DAT6/\ + MUX_VAL(CP(MMC1_DAT7), (IEN \| PTU \| EN \| M0)) /MMC1_DAT7/\ + /Bluetooth/\ + MUX_VAL(CP(UART1_TX), (IDIS \| PTD \| DIS \| M0)) /UART1_TX/\ + MUX_VAL(CP(UART1_RTS), (IEN \| PTU \| DIS \| M4)) /GPIO_149/ \ + MUX_VAL(CP(UART1_CTS), (IEN \| PTU \| DIS \| M4)) /GPIO_150-MMC3_WP/\ + MUX_VAL(CP(UART1_RX), (IEN \| PTD \| DIS \| M0)) /UART1_RX/\ + MUX_VAL(CP(UART2_TX), (IDIS \| PTD \| DIS \| M0)) /UART2_TX/\ + MUX_VAL(CP(UART2_RX), (IEN \| PTD \| DIS \| M0)) /UART2_RX/\ + /Serial Interface/\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN \| PTU \| EN \| M4)) /GPIO_163/\ + MUX_VAL(CP(UART3_RTS_SD), (IEN \| PTU \| EN \| M4)) /GPIO_164 W2W_/\ + / BT_NRESET/\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN \| PTU \| EN \| M0)) /UART3_RX_IRRX/\ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS \| PTD \| DIS \| M0)) /UART3_TX_IRTX/\ + MUX_VAL(CP(HSUSB0_CLK), (IEN \| PTD \| DIS \| M0)) /HSUSB0_CLK/\ + MUX_VAL(CP(HSUSB0_STP), (IDIS \| PTU \| EN \| M0)) /HSUSB0_STP/\ + MUX_VAL(CP(HSUSB0_DIR), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DIR/\ + MUX_VAL(CP(HSUSB0_NXT), (IEN \| PTD \| DIS \| M0)) /HSUSB0_NXT/\ + MUX_VAL(CP(HSUSB0_DATA0), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA0/\ + MUX_VAL(CP(HSUSB0_DATA1), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA1/\ + MUX_VAL(CP(HSUSB0_DATA2), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA2/\ + MUX_VAL(CP(HSUSB0_DATA3), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA3/\ + MUX_VAL(CP(HSUSB0_DATA4), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA4/\ + MUX_VAL(CP(HSUSB0_DATA5), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA5/\ + MUX_VAL(CP(HSUSB0_DATA6), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA6/\ + MUX_VAL(CP(HSUSB0_DATA7), (IEN \| PTD \| DIS \| M0)) /HSUSB0_DATA7/\ + MUX_VAL(CP(I2C1_SCL), (IEN \| PTU \| EN \| M0)) /I2C1_SCL/\ + MUX_VAL(CP(I2C1_SDA), (IEN \| PTU \| EN \| M0)) /I2C1_SDA/\ + MUX_VAL(CP(I2C2_SCL), (IEN \| PTU \| EN \| M4)) /GPIO_168/\ + / - USBH_CPEN/\ + MUX_VAL(CP(I2C2_SDA), (IEN \| PTU \| EN \| M4)) /GPIO_183/\ + / - USBH_RESET/\ + MUX_VAL(CP(I2C3_SCL), (IEN \| PTU \| EN \| M0)) /I2C3_SCL/\ + MUX_VAL(CP(I2C3_SDA), (IEN \| PTU \| EN \| M0)) /I2C3_SDA/\ + MUX_VAL(CP(I2C4_SCL), (IEN \| PTU \| EN \| M0)) /I2C4_SCL/\ + MUX_VAL(CP(I2C4_SDA), (IEN \| PTU \| EN \| M0)) /I2C4_SDA/\ + MUX_VAL(CP(HDQ_SIO), (IDIS \| PTU \| EN \| M4)) /HDQ_SIO/\ + MUX_VAL(CP(MCSPI1_CLK), (IEN \| PTD \| DIS \| M0)) /McSPI1_CLK/\ + MUX_VAL(CP(MCSPI1_SIMO), (IEN \| PTD \| DIS \| M0)) /McSPI1_SIMO /\ + MUX_VAL(CP(MCSPI1_SOMI), (IEN \| PTD \| DIS \| M0)) /McSPI1_SOMI /\ + MUX_VAL(CP(MCSPI1_CS0), (IEN \| PTD \| EN \| M0)) /McSPI1_CS0/\ + MUX_VAL(CP(MCSPI1_CS1), (IDIS \| PTD \| EN \| M0)) /McSPI1_CS1/\ + MUX_VAL(CP(MCSPI1_CS2), (IEN \| PTU \| DIS \| M4)) /GPIO_176 /\ + / - LAN_INTR /\ + MUX_VAL(CP(MCSPI1_CS3), (IEN \| PTD \| DIS \| M3)) /HSUSB2_DATA2/\ + MUX_VAL(CP(MCSPI2_CLK), (IEN \| PTD \| DIS \| M3)) /HSUSB2_DATA7/\ + MUX_VAL(CP(MCSPI2_SIMO), (IEN \| PTD \| DIS \| M3)) /HSUSB2_DATA4/\ + MUX_VAL(CP(MCSPI2_SOMI), (IEN \| PTD \| DIS \| M3)) /HSUSB2_DATA5/\ + MUX_VAL(CP(MCSPI2_CS0), (IEN \| PTD \| DIS \| M3)) /HSUSB2_DATA6/\ + MUX_VAL(CP(MCSPI2_CS1), (IEN \| PTD \| DIS \| M3)) /HSUSB2_DATA3/\ + /Control and debug /\ + MUX_VAL(CP(SYS_32K), (IEN \| PTD \| DIS \| M0)) /SYS_32K/\ + MUX_VAL(CP(SYS_CLKREQ), (IEN \| PTD \| DIS \| M0)) /SYS_CLKREQ/\ + MUX_VAL(CP(SYS_NIRQ), (IEN \| PTU \| EN \| M0)) /SYS_nIRQ/\ + MUX_VAL(CP(SYS_BOOT0), (IEN \| PTD \| DIS \| M4)) /GPIO_2/\ + MUX_VAL(CP(SYS_BOOT1), (IEN \| PTD \| DIS \| M4)) /GPIO_3 /\ + MUX_VAL(CP(SYS_BOOT2), (IEN \| PTD \| DIS \| M4)) /GPIO_4 - MMC1_WP/\ + MUX_VAL(CP(SYS_BOOT3), (IEN \| PTD \| DIS \| M4)) /GPIO_5/\ + MUX_VAL(CP(SYS_BOOT4), (IEN \| PTD \| DIS \| M4)) /GPIO_6/\ + MUX_VAL(CP(SYS_BOOT5), (IEN \| PTD \| DIS \| M4)) /GPIO_7/\ + MUX_VAL(CP(SYS_BOOT6), (IDIS \| PTD \| DIS \| M4)) /GPIO_8/\ + MUX_VAL(CP(SYS_OFF_MODE), (IEN \| PTD \| DIS \| M0)) /SYS_OFF_MODE/\ + MUX_VAL(CP(SYS_CLKOUT1), (IEN \| PTU \| EN \| M4)) /GPIO_10/\ + MUX_VAL(CP(SYS_CLKOUT2), (IEN \| PTU \| EN \| M4)) /GPIO_186/\ + MUX_VAL(CP(ETK_CLK_ES2), (IEN \| PTU \| EN \| M2)) /MMC3_CLK/\ + MUX_VAL(CP(ETK_CTL_ES2), (IEN \| PTU \| EN \| M2)) /MMC3_CMD/\ + MUX_VAL(CP(ETK_D0_ES2), (IEN \| PTU \| EN \| M4)) /GPIO_14/\ + MUX_VAL(CP(ETK_D1_ES2), (IEN \| PTD \| EN \| M4)) /GPIO_15 - X_GATE/\ + MUX_VAL(CP(ETK_D2_ES2), (IEN \| PTU \| EN \| M4)) /GPIO_16/\ + / - W2W_NRESET/\ + MUX_VAL(CP(ETK_D3_ES2), (IEN \| PTU \| EN \| M2)) /MMC3_DAT3/\ + MUX_VAL(CP(ETK_D4_ES2), (IEN \| PTU \| EN \| M2)) /MMC3_DAT0/\ + MUX_VAL(CP(ETK_D5_ES2), (IEN \| PTU \| EN \| M2)) /MMC3_DAT1/\ + MUX_VAL(CP(ETK_D6_ES2), (IEN \| PTU \| EN \| M2)) /MMC3_DAT2/\ + MUX_VAL(CP(ETK_D7_ES2), (IEN \| PTU \| EN \| M4)) /GPIO_21/\ + MUX_VAL(CP(ETK_D8_ES2), (IEN \| PTU \| EN \| M4)) /GPIO_22/\ + MUX_VAL(CP(ETK_D9_ES2), (IEN \| PTU \| EN \| M4)) /GPIO_23/\ + MUX_VAL(CP(ETK_D10_ES2), (IDIS \| PTD \| DIS \| M3)) /HSUSB2_CLK/\ + MUX_VAL(CP(ETK_D11_ES2), (IDIS \| PTD \| DIS \| M3)) /HSUSB2_STP/\ + MUX_VAL(CP(ETK_D12_ES2), (IEN \| PTD \| DIS \| M3)) /HSUSB2_DIR/\ + MUX_VAL(CP(ETK_D13_ES2), (IEN \| PTD \| DIS \| M3)) /HSUSB2_NXT/\ + MUX_VAL(CP(ETK_D14_ES2), (IEN \| PTD \| DIS \| M3)) /HSUSB2_DATA0/\ + MUX_VAL(CP(ETK_D15_ES2), (IEN \| PTD \| DIS \| M3)) /HSUSB2_DATA1/\ + / die to die /\ + MUX_VAL(CP(D2D_MCAD1), (IEN \| PTD \| EN \| M0)) /d2d_mcad1/\ + MUX_VAL(CP(D2D_MCAD2), (IEN \| PTD \| EN \| M0)) /d2d_mcad2/\ + MUX_VAL(CP(D2D_MCAD3), (IEN \| PTD \| EN \| M0)) /d2d_mcad3/\ + MUX_VAL(CP(D2D_MCAD4), (IEN \| PTD \| EN \| M0)) /d2d_mcad4/\ + MUX_VAL(CP(D2D_MCAD5), (IEN \| PTD \| EN \| M0)) /d2d_mcad5/\ + MUX_VAL(CP(D2D_MCAD6), (IEN \| PTD \| EN \| M0)) /d2d_mcad6/\ + MUX_VAL(CP(D2D_MCAD7), (IEN \| PTD \| EN \| M0)) /d2d_mcad7/\ + MUX_VAL(CP(D2D_MCAD8), (IEN \| PTD \| EN \| M0)) /d2d_mcad8/\ + MUX_VAL(CP(D2D_MCAD9), (IEN \| PTD \| EN \| M0)) /d2d_mcad9/\ + MUX_VAL(CP(D2D_MCAD10), (IEN \| PTD \| EN \| M0)) /d2d_mcad10/\ + MUX_VAL(CP(D2D_MCAD11), (IEN \| PTD \| EN \| M0)) /d2d_mcad11/\ + MUX_VAL(CP(D2D_MCAD12), (IEN \| PTD \| EN \| M0)) /d2d_mcad12/\ + MUX_VAL(CP(D2D_MCAD13), (IEN \| PTD \| EN \| M0)) /d2d_mcad13/\ + MUX_VAL(CP(D2D_MCAD14), (IEN \| PTD \| EN \| M0)) /d2d_mcad14/\ + MUX_VAL(CP(D2D_MCAD15), (IEN \| PTD \| EN \| M0)) /d2d_mcad15/\ + MUX_VAL(CP(D2D_MCAD16), (IEN \| PTD \| EN \| M0)) /d2d_mcad16/\ + MUX_VAL(CP(D2D_MCAD17), (IEN \| PTD \| EN \| M0)) /d2d_mcad17/\ + MUX_VAL(CP(D2D_MCAD18), (IEN \| PTD \| EN \| M0)) /d2d_mcad18/\ + MUX_VAL(CP(D2D_MCAD19), (IEN \| PTD \| EN \| M0)) /d2d_mcad19/\ + MUX_VAL(CP(D2D_MCAD20), (IEN \| PTD \| EN \| M0)) /d2d_mcad20/\ + MUX_VAL(CP(D2D_MCAD21), (IEN \| PTD \| EN \| M0)) /d2d_mcad21/\ + MUX_VAL(CP(D2D_MCAD22), (IEN \| PTD \| EN \| M0)) /d2d_mcad22/\ + MUX_VAL(CP(D2D_MCAD23), (IEN \| PTD \| EN \| M0)) /d2d_mcad23/\ + MUX_VAL(CP(D2D_MCAD24), (IEN \| PTD \| EN \| M0)) /d2d_mcad24/\ + MUX_VAL(CP(D2D_MCAD25), (IEN \| PTD \| EN \| M0)) /d2d_mcad25/\ + MUX_VAL(CP(D2D_MCAD26), (IEN \| PTD \| EN \| M0)) /d2d_mcad26/\ + MUX_VAL(CP(D2D_MCAD27), (IEN \| PTD \| EN \| M0)) /d2d_mcad27/\ + MUX_VAL(CP(D2D_MCAD28), (IEN \| PTD \| EN \| M0)) /d2d_mcad28/\ + MUX_VAL(CP(D2D_MCAD29), (IEN \| PTD \| EN \| M0)) /d2d_mcad29/\ + MUX_VAL(CP(D2D_MCAD30), (IEN \| PTD \| EN \| M0)) /d2d_mcad30/\ + MUX_VAL(CP(D2D_MCAD31), (IEN \| PTD \| EN \| M0)) /d2d_mcad31/\ + MUX_VAL(CP(D2D_MCAD32), (IEN \| PTD \| EN \| M0)) /d2d_mcad32/\ + MUX_VAL(CP(D2D_MCAD33), (IEN \| PTD \| EN \| M0)) /d2d_mcad33/\ + MUX_VAL(CP(D2D_MCAD34), (IEN \| PTD \| EN \| M0)) /d2d_mcad34/\ + MUX_VAL(CP(D2D_MCAD35), (IEN \| PTD \| EN \| M0)) /d2d_mcad35/\ + MUX_VAL(CP(D2D_MCAD36), (IEN \| PTD \| EN \| M0)) /d2d_mcad36/\ + MUX_VAL(CP(D2D_CLK26MI), (IEN \| PTD \| DIS \| M0)) /d2d_clk26mi/\ + MUX_VAL(CP(D2D_NRESPWRON), (IEN \| PTD \| EN \| M0)) /d2d_nrespwron/\ + MUX_VAL(CP(D2D_NRESWARM), (IEN \| PTU \| EN \| M0)) /d2d_nreswarm /\ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN \| PTD \| DIS \| M0)) /d2d_arm9nirq /\ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN \| PTD \| DIS \| M0)) /d2d_uma2p6fiq/\ + MUX_VAL(CP(D2D_SPINT), (IEN \| PTD \| EN \| M0)) /d2d_spint/\ + MUX_VAL(CP(D2D_FRINT), (IEN \| PTD \| EN \| M0)) /d2d_frint/\ + MUX_VAL(CP(D2D_DMAREQ0), (IEN \| PTD \| DIS \| M0)) /d2d_dmareq0/\ + MUX_VAL(CP(D2D_DMAREQ1), (IEN \| PTD \| DIS \| M0)) /d2d_dmareq1/\ + MUX_VAL(CP(D2D_DMAREQ2), (IEN \| PTD \| DIS \| M0)) /d2d_dmareq2/\ + MUX_VAL(CP(D2D_DMAREQ3), (IEN \| PTD \| DIS \| M0)) /d2d_dmareq3/\ + MUX_VAL(CP(D2D_N3GTRST), (IEN \| PTD \| DIS \| M0)) /d2d_n3gtrst/\ + MUX_VAL(CP(D2D_N3GTDI), (IEN \| PTD \| DIS \| M0)) /d2d_n3gtdi/\ + MUX_VAL(CP(D2D_N3GTDO), (IEN \| PTD \| DIS \| M0)) /d2d_n3gtdo/\ + MUX_VAL(CP(D2D_N3GTMS), (IEN \| PTD \| DIS \| M0)) /d2d_n3gtms/\ + MUX_VAL(CP(D2D_N3GTCK), (IEN \| PTD \| DIS \| M0)) /d2d_n3gtck/\ + MUX_VAL(CP(D2D_N3GRTCK), (IEN \| PTD \| DIS \| M0)) /d2d_n3grtck/\ + MUX_VAL(CP(D2D_MSTDBY), (IEN \| PTU \| EN \| M0)) /d2d_mstdby/\ + MUX_VAL(CP(D2D_SWAKEUP), (IEN \| PTD \| EN \| M0)) /d2d_swakeup/\ + MUX_VAL(CP(D2D_IDLEREQ), (IEN \| PTD \| DIS \| M0)) /d2d_idlereq/\ + MUX_VAL(CP(D2D_IDLEACK), (IEN \| PTU \| EN \| M0)) /d2d_idleack/\ + MUX_VAL(CP(D2D_MWRITE), (IEN \| PTD \| DIS \| M0)) /d2d_mwrite/\ + MUX_VAL(CP(D2D_SWRITE), (IEN \| PTD \| DIS \| M0)) /d2d_swrite/\ + MUX_VAL(CP(D2D_MREAD), (IEN \| PTD \| DIS \| M0)) /d2d_mread/\ + MUX_VAL(CP(D2D_SREAD), (IEN \| PTD \| DIS \| M0)) /d2d_sread/\ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN \| PTD \| DIS \| M0)) /d2d_mbusflag/\ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN \| PTD \| DIS \| M0)) /d2d_sbusflag/\ + MUX_VAL(CP(SDRC_CKE0), (IDIS \| PTU \| EN \| M0)) /sdrc_cke0/\ + MUX_VAL(CP(SDRC_CKE1), (IDIS \| PTU \| EN \| M0)) /sdrc_cke1*/ #endif

dtran11

New Member
Posts:23

04 Feb 2013 12:32 PM
Here is the bitbake recipe for uboot if you need it. require u-boot.inc SRCREV = "190649fb4309d1bc0fe7732fd0f951cb6440f935" PV = "2012.07" PR = "r1" SRC_URI = "git://git.denx.de/u-boot.git;branch=master;protocol=git \ file://uboot-fixes.patch;apply=yes \ file://uboot-fast-boot.patch;apply=yes \ "

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