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Last Post 24 Oct 2012 02:38 PM by  nathank
Power Sequencing / Level Shifting / Ioff issues...
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ken.kollet@ctc-control.com
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11 Oct 2012 09:04 AM
    Hi,
    Can someone please confirm this for me:
    1) I just spun a board with a SOM OMAP138, and I left the IO_VOLT_SEL pin floating, so that the IO signals are 3.3V.
    2) I then have some ICs (RS485 transceivers, external SRAM) on my custom baseboard that are powered by a different +3.3V (which share the same digital ground as the SOM).
    The question is that even though both the SOM’s IO signals and the external circuitry’s IO signals are at +3.3V, do I still need the “dual rail” level shifters (similar to the SN74AVC16T245DGG used on the LogicPD’s baseboard) to eliminate power sequencing (I.e. Ioff) issues? For example, I would assume that if the +3.3V on the SOM came up first, that there would be a possible latch-up condition do the parasitic diodes in the external circuitry going to a rail which is less than the SOM’s +3.3V. Or, vise-versa…

    Thanks.
    nathank
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    24 Oct 2012 02:38 PM
    Hi

    That is a valid concern with 2 different power supplies. If you can ensure that the power supplies start up at about the same time (I would say within milliseconds of eachother) you should be OK. The Logic PD baseboard uses MSTR_nRST_3.3_1.8 to control this timing. I would suggest looking at how that is implemented on the Logic board and copy that design if possible.

    Nate
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