I got this patch from the guy who maintains the M5329 MTD drivers. It should patch against the 2.6.17 kernel relatively ok.
diff U3b Z:/uClinux_linux-2.6.x_arch/m68knommu/platform/532x/config.c@@/main/anta_EMV_Mod3/1 Z:/wipe/linux-2.6.x/arch/m68knommu/platform/532x/config.c@@/main/anta_EMV_Mod3/2
--- Z:/uClinux_linux-2.6.x_arch/m68knommu/platform/532x/config.c@@/main/anta_EMV_Mod3/1 Fri Sep 15 16:59:33 2006
+++ Z:/wipe/linux-2.6.x/arch/m68knommu/platform/532x/config.c@@/main/anta_EMV_Mod3/2 Mon Oct 02 14:41:44 2006
@@ -47,6 +47,21 @@
/***************************************************************************/
+int sys_clk_khz = 0;
+int sys_clk_mhz = 0;
+
+void wtm_init(void);
+void scm_init(void);
+void gpio_init(void);
+void fbcs_init(void);
+void sdramc_init(void);
+int clock_pll (int fsys, int flags);
+int clock_limp (int);
+int clock_exit_limp (void);
+int get_sys_clock (void);
+
+/***************************************************************************/
+
/*
* DMA channel base address table.
*/
@@ -91,6 +106,9 @@
void config_BSP(char *commandp, int size)
{
+ sys_clk_khz = get_sys_clock();
+ sys_clk_mhz = sys_clk_khz/1000;
+
mcf_setimr(MCFSIM_IMR_MASKALL);
#if defined(CONFIG_BOOTPARAM)
@@ -168,24 +186,9 @@
#define NAND_FLASH_ADDRESS (0xD0000000)
-int sys_clk_khz = 0;
-int sys_clk_mhz = 0;
-
-void wtm_init(void);
-void scm_init(void);
-void gpio_init(void);
-void fbcs_init(void);
-void sdramc_init(void);
-int clock_pll (int fsys, int flags);
-int clock_limp (int);
-int clock_exit_limp (void);
-int get_sys_clock (void);
asmlinkage void __init sysinit(void)
{
- sys_clk_khz = clock_pll(0, 0);
- sys_clk_mhz = sys_clk_khz/1000;
-
wtm_init();
scm_init();
gpio_init();
@@ -234,14 +237,14 @@
/* Initialize latch to drive signals to inactive states */
*((u16 *)(0x10080000)) = 0xFFFF;
- /* External SRAM */
- MCF_FBCS1_CSAR = EXT_SRAM_ADDRESS;
- MCF_FBCS1_CSCR = (MCF_FBCS_CSCR_PS_16
- | MCF_FBCS_CSCR_AA
- | MCF_FBCS_CSCR_SBM
- | MCF_FBCS_CSCR_WS(1));
- MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_512K
- | MCF_FBCS_CSMR_V);
+// /* External SRAM */
+// MCF_FBCS1_CSAR = EXT_SRAM_ADDRESS;
+// MCF_FBCS1_CSCR = (MCF_FBCS_CSCR_PS_16
+// | MCF_FBCS_CSCR_AA
+// | MCF_FBCS_CSCR_SBM
+// | MCF_FBCS_CSCR_WS(1));
+// MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_512K
+// | MCF_FBCS_CSMR_V);
/* Boot Flash connected to FBCS0 */
MCF_FBCS0_CSAR = FLASH_ADDRESS;
diff U3b Z:/uClinux_linux-2.6.x_drivers/mtd/nand/m5329.c@@/main/anta_EMV_Mod3/1 Z:/wipe/linux-2.6.x/drivers/mtd/nand/m5329.c@@/main/anta_EMV_Mod3/2
--- Z:/uClinux_linux-2.6.x_drivers/mtd/nand/m5329.c@@/main/anta_EMV_Mod3/1 Fri Sep 15 17:48:45 2006
+++ Z:/wipe/linux-2.6.x/drivers/mtd/nand/m5329.c@@/main/anta_EMV_Mod3/2 Fri Sep 29 09:21:32 2006
@@ -36,6 +36,9 @@
/*
* Values specific to the SPIA board (used with EP7212 processor)
*/
+#define NAND_FLASH_CE ((u16 *)(0x10080000))
+#define NCE_LOW_VAL 0xfbfb
+#define NCE_HIGH_VAL 0xffff
#define NAND_FLASH_ADDRESS 0xd0000000 /* Fash address mapping */
#define CLE_ADDR_BIT 4
@@ -90,10 +93,12 @@
m5329_fio_base &= ~(1<<ALE_ADDR_BIT);
break;
case NAND_CTL_SETNCE:
- m5329_fio_base &= ~(1<<NCE_ADDR_BIT);
+ *NAND_FLASH_CE = NCE_LOW_VAL;
+// m5329_fio_base &= ~(1<<NCE_ADDR_BIT);
break;
case NAND_CTL_CLRNCE:
- m5329_fio_base |= 1<NCE_ADDR_BIT;
+ *NAND_FLASH_CE = NCE_HIGH_VAL;
+// m5329_fio_base |= 1<NCE_ADDR_BIT;
break;
}
/* Set address of NAND IO lines */
@@ -135,6 +140,8 @@
/* Link the private data with the MTD structure */
m5329_mtd->priv = this;
+
+ *NAND_FLASH_CE = NCE_HIGH_VAL;
/* Set address of NAND IO lines */
this->IO_ADDR_R = (void __iomem *) m5329_fio_base;