Brianna,
The CPLD logic for the CF card nIOWR signal is driven by the nWE signal on the CPU which is the netname uP_nWR in the schematic. Make sure the CPU chip select register is configured to asserte nWE during writes. Also, refer to CF timing specification for minimum time required for nWE assertion for CF writes. It states a minimum of 150nS.
Check out the timing diagram on page 60 of this document:
http://www.compactflash.org/cfspc3_0.pdf
Also, if you have access to an oscilloscope, how long is nIOWR being asserted currently?
-Kurt