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Last Post 13 Aug 2003 12:11 PM by  Anonymous
Don't get cpld i2s DMA output
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junli
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11 Aug 2003 06:51 PM
    On LH79520 card engine cpld interface specification – page 13, 4.7 Codec I2S Interface, 2. Once the CPLD receives the bit-clock from the codec, the CPLD will generate a DMA request every sample period.

    I have generated and measured the bit-block signal I2S_BCK as 2.83Mhz and LRCIN signal as 44.3Khz, but I don’t get the DMA request signal uP_DREQ0 at all. Please instruct is there any other register I need to set to get this uP_DREQ0 out. The CPLD version is 11.

    Anonymous
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    13 Aug 2003 12:11 PM
    The io controller interface specification was written before we became aware of this app note:
    http://www.sharpsma.com/p...xxx_StaticMemory.pdf

    since then we have added a barrier function between each access to the spi interface in the cpld in order to make sure that the chip select line
    toggles.

    code snippet:
    void
    barrier(void)
    {
    /* flash is guaranteed not to be cached, and to be in
    * a different region from the cpld */
    volatile u_int tmp = *(volatile u_int *)MEMAP_BASE_FLASH;
    tmp = 1;
    }

    code snippet:

    barrier();

    /* load spi data into shift register */
    REG16(dev->data_reg) = src[i];

    barrier();

    /* write out the command */
    REG16(dev->control_reg) =
    (CPLD_CE_SPI_CNTL_LOAD_REG | dev->chip_select);

    barrier();

    The next version of the io spec will include the updated information.
    An errata to the current io spec should be posted shortly.

    sorry for any inconvience this caused. i think it will solve your problems.

    for reference, here are the codec configuration commands we are using to test the codec:
    /* touch_codec measurement commands */
    /* line off, 'x' 1, 'x' 1, dac on, out on, osc on, clk on, 'off' on, 'x' 0 */
    static const u_int16_t PWR_ON = 0x0c07; /* power down control 0x0110*/
    /* FOR 0x10: I2S format, MSB first, left -1 aligned, */
    /* IWL 0x00: input bit length 16 bits, */
    /* LRP 0x0 : right channel on, LRCIN high, LRSWAP 0x0: disabled, */
    /* MS 0x1 : Master */
    static const u_int16_t IF_FMT_CONF = 0x0e42;/* dig audio intfc format 0x0111 */
    static const u_int16_t IF_ON = 0x1201;/* dig intfc activation 0x1001 - ON */
    /* all da path control bits set to 0 for no muting and de-emphasis control*/
    static const u_int16_t DACM_DIS = 0x0a00;/* dig audio path cntrl 0x0101 */


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