Something like this in your low level startup code. This is lifted from one of the Freescale samples.
/* NOTE! This clock configuration code should NOT be executed from SDRAM */
/* Enter limp mode, weak SSI pullups, USB from PLL/4 for 240MHz */
move.l #MCF_CCM_MISCCR, a0
move.w #0x10F3,(a0)
/* Configure PLL settings for 240Mhz */
move.l #MCF_PLL_PODR, a0
move.b #0x26,(a0) /* CPUDIV = 2, BUSDIV = 6 */
move.l #MCF_PLL_PFDR, a0
move.b #0x78,(a0) /* 16MHz * 0x78 / 8 = 240MHz */
move.l #MCF_PLL_PLLCR, a0
move.b #0x00,(a0) /* DITHEN = 0 Dithering Disabled */
move.l #MCF_PLL_PMDR, a0
move.b #0x00,(a0) /* Dither Modulation Divider */
/* Exit limp mode, weak SSI pullups, USB from PLL/4 for 240MHz */
move.l #MCF_CCM_MISCCR, a0
move.w #0x00F3,(a0)
222:
/* Wait for PLL lock */
move.w MCF_CCM_MISCCR, d0
btst #13, d0
beqs 222b