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Last Post 23 Jun 2017 08:08 AM by  Alex Roberts
Bare Metal Linker Script Memory Addressing Error
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Alex Roberts
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Posts:4


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22 Jun 2017 04:39 PM

    The DM3730.cmd linker script provided by TI defines the memory map as follows:

        SRAM:           o = 0x40200000  l = 0x00010000  /* 64kB Internal SRAM */
        CS0_SDRAM:      o = 0x80000000  l = 0x20000000  /* 512MB of external mDDR in CS0 */
        CS1_SDRAM:      o = 0xA0000000  l = 0x20000000  /* 512MB of external mDDR in CS1 */

    ......


        DDR0:           o = 0x80000000  l = 0x40000000  /* 1GB external DDR Bank 0 */
        DDR1:           o = 0xC0000000  l = 0x40000000  /* 1GB external DDR Bank 1 */

    I get an error because the map for CS0/CS1 overlaps with the map for DDR0 and DDR1. I two versions of the Torpedo SoM, one with 256 MB DDR / 512 MB Flash NAND and one with 512MB DDR / 512 MB Flash NAND.

    What is the correct memory mapping for these modules? Also, what is the starting address for the NAND?

    It is my understanding from the DM3730 that the DDR is connected to the SDRAM controller and addressing should start at 0x80000000. What I don't understand and can't seem to find is where the addressing starts for the NAND Flash.

    I'm looking at a bare metal application, so please no OS (Linux) related responses. Thanks!

    Adam Ford
    Advanced Member
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    Posts:793


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    23 Jun 2017 07:57 AM
    Do you have the DM3730 Technical Reference Manual? (http://www.ti.com/lit/pdf/sprugn4)

    You may have to log into TI.com to be able to download it.

    The NAND chip Select pins can be programmed as to their offset and size. Basically, CS0 is assigned to a memory bank and CS1 is assigned to a different one.

    As a point of reference, Linux 4.11 defines the addresses as:

    0x30000000 0x1000000 /* CS0: 16MB for NAND */
    0x2c000000 0x1000000>; /* CS1: 16MB for LAN9221 */

    Where adderss is the 1st number, and size is the 2nd number.
    I know you don't want a Linux answer, but I know these settings work. I am not sure if you're using a bootloader to launch your bare metal application, but our U-Boot implementation can read register values, so if you want to get a whole dump of how the GPMC registers are configured, I would suggest looking at that. Table Table 10-28 of the Technical Reference manual shows all the different registers. The GPMC bus is more than just memory addresses, it also sets timings, multiplexing, and others, so without knowing exactly what you're trying to do it's a little difficult to give too much detail. Each GPMC CS pin has its own set of CONFIG registers so the timings.


    CS0 for DDR is always 0x80000000, but the the Memory offset for C1 of the DDR controller is programmable.

    Check out section 10.2.4.4.1 of the Technical Reference manual to define the CS0 size (SDRC_MCFG_0[17:8] RAMSIZE) and configure the CS1 parameters.

    I did a memory dump on SDRC_MCFG_0 [bits 8-17] and the RAM sizes returns 0x80 which means it's 256 MB assigned to CS0

    Hopefully that will help.

    adam




    Alex Roberts
    New Member
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    Posts:4


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    23 Jun 2017 08:08 AM

    Adam,

    That definitely helps. I do have a copy of TRM and have been combing through it. Based on the code comments in the TI provided linker script, it seems like they are defining the DDR addresses twice. I've commented out one pair and adjusted the size of the banks accordingly to match the board versions I have. I will take a look at dumping the GPMC registers from uBoot.

    Thanks.

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