Do you have the DM3730 Technical Reference Manual? (
http://www.ti.com/lit/pdf/sprugn4) You may have to log into TI.com to be able to download it.
The NAND chip Select pins can be programmed as to their offset and size. Basically, CS0 is assigned to a memory bank and CS1 is assigned to a different one.
As a point of reference, Linux 4.11 defines the addresses as:
0x30000000 0x1000000 /* CS0: 16MB for NAND */
0x2c000000 0x1000000>; /* CS1: 16MB for LAN9221 */
Where adderss is the 1st number, and size is the 2nd number.
I know you don't want a Linux answer, but I know these settings work. I am not sure if you're using a bootloader to launch your bare metal application, but our U-Boot implementation can read register values, so if you want to get a whole dump of how the GPMC registers are configured, I would suggest looking at that. Table Table 10-28 of the Technical Reference manual shows all the different registers. The GPMC bus is more than just memory addresses, it also sets timings, multiplexing, and others, so without knowing exactly what you're trying to do it's a little difficult to give too much detail. Each GPMC CS pin has its own set of CONFIG registers so the timings.
CS0 for DDR is always 0x80000000, but the the Memory offset for C1 of the DDR controller is programmable.
Check out section 10.2.4.4.1 of the Technical Reference manual to define the CS0 size (SDRC_MCFG_0[17:8] RAMSIZE) and configure the CS1 parameters.
I did a memory dump on SDRC_MCFG_0 [bits 8-17] and the RAM sizes returns 0x80 which means it's 256 MB assigned to CS0
Hopefully that will help.
adam