thermal analysis of omap dm3730 with POP

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Last Post 02 Dec 2016 03:10 PM by thomas caltabellotta

thermal analysis of omap dm3730 with POP

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thomas caltabellotta

New Member
Posts:10

18 Nov 2016 02:33 PM
Chapter 5 of white paper 540, DM3730/AM3703 SOM-LV Thermal Management points out that heat can be conducted out the top through of the SOM-LV through the PoP memory package.Table 5.1 presents some thermal dissipation data generated by Logic PD. However, this table is not detailed enough to allow me to calculate an effective junction to case thermal resistance through the memory. Is it possible to get more detailed data? Ideally, I would need to know 1. Ambient Air Temperature 2. Thermal interface material and thickness, or TIM thermal resistance Thank you very much. Best regards, Tom

Adam Ford

Advanced Member
Posts:794

21 Nov 2016 11:04 AM
I put in the request with one of the electrical Engineers who worked on this SOM. One of the guys is on vacation this week due the holiday, so it's going to take me a little longer to get back. The ambient temperature is usually between 68 and 72 degrees F, but I'm still digging into it. adam

thomas caltabellotta

New Member
Posts:10

21 Nov 2016 11:16 AM
Thanks Adam!

thomas caltabellotta

New Member
Posts:10

28 Nov 2016 12:25 PM
Adam, do you have an update for me on this subject? Best regards, Tom

Adam Ford

Advanced Member
Posts:794

28 Nov 2016 01:15 PM
His calendar shows he is still out of the office. I sent him a followup e-mail. adam

Adam Ford

Advanced Member
Posts:794

28 Nov 2016 01:41 PM
One of you colleagues was asking questions about the Torpedo + Wireless, and I notice you referenced the SOM-LV. Are you using the SOM-LV, the Torpedo + Wireless or both? adam

Adam Ford

Advanced Member
Posts:794

28 Nov 2016 01:49 PM
The DM3730 and PoP packages in the Torpedo + Wireless are the same on the SOM-LV. The Torpedo + Wireless thermal document is located: http://support.logicpd.co...rtalid=0&EntryId=656 Looking through the section 6 of the document, it shows the ambient temperature was 24C +/1 1C It also lists the The gap pad used was a Thermally Conductive Interface Pad from 3M (5591S). This gap pad has a thermal conductivity of 1.0 W/m-K

thomas caltabellotta

New Member
Posts:10

28 Nov 2016 02:36 PM
Can you please make that document available to me? I am blocked from downloading it. I believe it is white paper WP530. Thanks, Tom

Adam Ford

Advanced Member
Posts:794

28 Nov 2016 02:47 PM
I believe you should have access now, please let me know if you don't, and I'll try again. adam

thomas caltabellotta

New Member
Posts:10

01 Dec 2016 11:36 AM
Adam, First of all, thank you for giving me access to the article, it was very helpful. Based on the information currently available to me, I'm estimating that the junction to case (through the PoP) thermal resistance is 16°C/W. However, this is a rough guess and neglects the board construction and Junction to board thermal resistance. TI gives us a value for theta JB. If I can convince you to provide me average in-plane and through the board thermal conductivity for the SOM-LV board, I can use that along with your published data to come up with a better estimate of theta-jc, an estimate that i would be more than happy to share with you guys. What do you say? I would also need to know if the board was conduction cooled or convection cooled in your experiments. Best Regards, Tom

Adam Ford

Advanced Member
Posts:794

01 Dec 2016 12:36 PM
I am going to have to ask our electrical engineer some of these questions, but I do know the at the normal method for running temperature testing is done using our temp chamber which would heat and cool through convection. adam

Adam Ford

Advanced Member
Posts:794

02 Dec 2016 07:15 AM
I don't know that we have the thermal conductivity of the PCB itself. Our electrical engineer said we can give you board stackup for the SOM-LV, and I can ask our board fabricator for the material information. Would that work for you? adam

thomas caltabellotta

New Member
Posts:10

02 Dec 2016 08:23 AM
yes, that would be great! the other piece of information i would need, if it's not too much trouble, is the number and sizxe of plated thru-holes, and the plating thickness. FR4 is a horrible thermal conductor. the plated thru holes have a great impact on the average through the board conductivity. Of course, I would share my calculations with you. Thank-you Adam! Tom

Adam Ford

Advanced Member
Posts:794

02 Dec 2016 02:54 PM
I have the stackup on paper, but I have requested to get the real-world numbers from the PCB fabricator. Once I hear back from the PCB fabricator, I'll privately e-mail you the information. I have your e-mail address from our support system. adam

Adam Ford

Advanced Member
Posts:794

02 Dec 2016 02:58 PM
FYI, the ideal stackup information is here: https://support.logicpd.com/DesktopModules/Bring2mind/DMX/Download.aspx?portalid=0&EntryId=705 Open the SOM-LV Layout PDF, and turn to page 15. You'll see the stackup and the quantity of plated through-holes. adam

thomas caltabellotta

New Member
Posts:10

02 Dec 2016 03:10 PM
thanks Adam!! This is perfect!!

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