I'm working on MCF5329EVB and I found a problem (?) with the connection of FlexBus Transfer Acknowledge (/TA) from Compact Flash to the CPU.
Looking at the schematics of the baseboard, the nCHRDY signal is connected to pin -WAIT (42) of the compact flash (page 5) and it ends on page 2 at 144PIN MCF5329 engine card connector (also on page 10 test-point). Looking at the schematics of the MCF5329 engine can be seen that the signal nCHRDY from page 2 ends in a logic inverter (SN74ALVC14DGVR) on page 7, where the output of inverter is called CHRDY_INVRT. This signal is connected to the test point (p. 11) and to gate of a MOSFET on the same page at the top. The drain of the MOSFET is connected to the signal nWAIT (?) that is connected, via pull-up, to the ColdFire /TA pin .

In other words, the signal connected to the ColdFire /TA is the same of /WAIT signal of the Compact Flash.

The two signals, however, have completely different meanings ... rather the opposite!

Compact Flash /WAIT
The /WAIT signal is driven low by the CompactFlash Storage Card or CF+ Card to signal the host to delay completion of a memory or I/O cycle that is in progress.

ColdFire /TA
This signal indicates the external data transfer is complete. When the processor recognizes FB_TA during a read cycle, it latches the data and then terminates the bus cycle. When the processor recognizes FB_TA during a write cycle, the bus cycle is terminated.

Reading the document "MCF5329-10 Hardware Specification", at page 15 you can read this:
"When pulled low, the nCHRDY signal generates a low on the uP_nWAIT signal to the processor, extending the length of the current cycle beyond the programmed internal wait states"

But this is FALSE!!! The uP_nWAIT is connected to /TA FlexBUS pin and this signal indicates the external data transfer is complete! Not a wait condition!!!

It is my opinion that the logic that manage WAIT (Compact Flash) and /TA (ColdFire) must be changed.

Could you kindly help me to solve this problem?
Thank you and good day!