dctoronto ,

Thanks for the notice, we will be shortly posting revision 105 to the website, check back in a while for a updated version. Also be aware that the part number will be changing, these changes will be listed on the schematic.

-Russellm

Russell,
The latest PCMCIA ref design is dated 6/25/04 but is rev 104. Does this contain the aforementioned changes? If not, when do you think 105 will be available?

The readme file for the PCMCIA driver mentions I/O support is only available for the "Primary" slot, SlotB. Is this because of driver limitations or limitations in the hardware ref design?

Is the primary slot referred to in the driver readme file, slot a or slot b in the ref design?

We need to have PCMCIA I/O functionality in our board and the hardware guy wants to make sure this is all going to play together.

Thanks

Joe

jjfitzy,

The design should be posted today.
It has been released as soon as the web team gets time, it will be available.

-Russ

Thanks Russ.

What about the other questions?? Any ideas?

Joe

jjfitzy,

The current HW design should support both IO and HW mode.
I have just finshed getting a Wireless CF card working with a PCMCIA adaptor in Both slots, using the lastest revision of the driver for the sharp A400.

The driver lacks dynamic timing information setup for I/O cards, using the CIS structure, but these can be customized through the registry for the both slots.

I believe Slot B is the primary slot.

-Russellm

Russ,

Again, thanks for the info. The reason for the question comes from the readme file from the beta_003 version of the driver:

3) Known Issues

--) SlotA (secondary slot) does not function with I/O cards
--) Insertion/ejection issue has been noted with MODEM cards in certain
circumstances (related to dial state)

So, we were wondering whether it was a hardware issue or an issue with driver.

Joe

Russ,

Rereading this post, another question is:

On the ref schematic, which ref A or B refers to the "Primary" slot referenced in the readme.txt file for the pcmcia driver for I/O and memory modes? Just wanna be sure!

Also, PCM_RDYA connects to RSVD_1 for the interupt on slot A. Is there a corresponding interupt for the "B" lines?

Thanks

Joe

jjfitzy,

The Interrupts for Slot A have not been fully implemented int he BETA 004 driver yet. So this is a software limitation, so if a person were to run a polling mode driver, I suppose it would work with Slot A, hehe.

I am looking into PCM_RDYA question. At this time I am not sure what the situation is. It should be noted this actual schematic has never been placed into full hardware design. Its "Theory" at the moment, most of our designs use CPLDs to handle all this logic, and thus we have not worried about this.

For your hardware guys, I would follow this loosely. Since this schematic has not been built and tested.

Slot B is the primary slot. PCM_RDYA goes to RSVD_1 and is directly routed to the processor. PCM_RDYB goes through the status buffers to the uP_PCC_RDY card engine interface signal and from their directly to the processor.

When SlotA status is read, the status buffer for SlotB is disabled and the on for SlotA is enabled - this results in the uP_PCC_RDY signal being set to PCM_RDYA momentarily. When SlotA status is read, the buffer is then switched back to the default position of reading SlotB status. During the time when the SlotA status buffers are enabled, interrupts are disabled for SlotB in the WinCE driver.

- Hans

Hans/Russ,

Thanks for your help. We'll keep you up to date on the progress.

Russ, your post mentions BETA 004. When is it going to be available?

Joe

Joe - I don't think Russ has seen your response yet, so I'll chime in - the beta_004 is posted now (has been up for a week or two).

Best of luck.

- Hans

Hans,

I must be missing something. The downloads page identifies the currnet driver as BETA_003.

Joe

I am just starting the h/w design for this i/f and would appreciate knowing if anyone has found any problems with the design.

I also have a fundamental question on the i/f signals. As I understand it, the signals are connected to the card engine connector labeled J1[A,B,C] on the LH7A400 Card Engine Schematics. The signal names do not seem to match up between the two schematics and I just want to make sure I am not missing something very basic here. Please correct me if I am wrong, but are these equivalent signals:

uP_A[25:0] == uPMMA[25:0]
uP_D[31:0] == uPMMD[31:0]

There are a number of control signals that also seem to be missing a source and seem to match the names of signals on J1B and J1C. I found equivalent names for some but not all.

Thanks for your help.
Terry Fowler