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Last Post 10 Nov 2003 01:24 PM by  Anonymous
Toggling Slow Peripherals Chip Select 6 lines
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10 Nov 2003 01:24 PM
    The LH7A400-10 IO Controller Spec provides instructions for using the Slow Peripherals Chip Select 6 (CS6) area: CompactFlash (CF), ISA-like BUS, Reserved On and Off board memory blocks, and open memory blocks.

    As the IO Controller Spec states, the address range of this area is 0x6000 0000 - 0x63FF FFFF. The CPLD decodes processor address lines uP_MA21-uP_MA25 into SLOW_nCS, CF_nCE, and nAEN.

    The decoding process takes:
    ISA address range --> nAEN line will toggle
    Compact Flach address range --> CF_nCE will toggle
    Chip Select 6 address other than valid CPLD registers --> slow_CS line will toggle.

    Reference CPLD IO controller spec document for valid and unused CPLD register addresses ranges.

    Regards,
    Andrew Wawra
    Logic Product Development
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