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Last Post 20 Oct 2008 06:34 AM by  joncastillo
Is anyone working with EPI Tools (Majic)
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jpavlik
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25 Jan 2006 07:26 AM
    I have a Majic jtag debugger and was trying to use the epiflash program on the pxa270 board. It seems as if it might read ok but writing is problematic. Anyone using this?
    mikea@logicpd.com
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    25 Jan 2006 12:12 PM
    I have not worked with the Majic JTAG device and can't offer much help there, but one quick thing is to check that you are enabling Flash for writes. This requires the use of the FL_VPEN bit in the CPLD's (I/O Controller) Card Engine Control Regiter. You are probably handling this already, but just wanted to be sure. [Information regarding this register can be found in the I/O controller spec]

    Thanks,
    -Mike
    jpavlik
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    25 Jan 2006 12:43 PM
    Thanks. It looks like the FL_VPEN bit is set already. This register is 00360036. That's strange actually, seems to be stating that one of the flash devices is busy?

    What does the duplicate word mean? i.e. the 0036 in low and high word.

    I can't seem to change this register. The code revision register is 000B000B
    mikea@logicpd.com
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    25 Jan 2006 01:01 PM
    The register is in a 16bit area, so you'll want to read and write to it as such.
    kurtl@logicpd.com
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    25 Jan 2006 01:07 PM
    The CPLD area must be setup as a 16bit wide area and use 16bit accesses for correct operation. It looks like in your case the CPU did 2 reads to the CPLD at 0xXXXX00 and 0xXXXX02 offset which will return the same result in the upper and lower half of your word. For example the revision register you read 32 bits, and got 0x000B000B - the true revision is 0x000B. The value is repeated because the register addresses in CPLD exist at more than one location because we use high order address lines to define their location in memory.

    For the value of 0x0036, double check the I/O controller spec for each bits definition. The correct interpretation of 0x0036 starting from MSB is like this:
    Upper eight bits = ignore.
    bit 7 = 0 which is reserved
    bit 6 = 0 which means FLASH_nCS asserts normally
    bit 5 = 1 which means external uP_STATUS1 signal is asserted high
    bit 4 = 1 which means external uP_STATUS2 signal is asserted high
    bit 3 = 0 which means FL_VPEN is holding the flash chip in write protect mode
    bit 2 = 1 which means upper data flash is ready
    bit 1 = 1 which means lower data flash is ready
    bit 0 = 0 which means wired LAN is power is enabled
    jpavlik
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    25 Jan 2006 02:43 PM
    Understood - I mistakenly didn't setup everything as 16 bit.

    As far as my binary interpretation, well, is it friday yet?
    mikea@logicpd.com
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    25 Jan 2006 02:48 PM
    It isn't Friday yet, but close enough.
    jpavlik
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    25 Jan 2006 03:26 PM
    Well, I'm getting closer, I can now erase but fill still seems to fail.
    joncastillo
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    20 Oct 2008 06:34 AM
    hi jpavlik, do you still visit the message board? Wondering if I could have a copy of your epi tools majic files. It's a used one I bought from an auction and it didn't come with any software. I'm working on the i.mx31 litekit.
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