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Last Post 13 Oct 2005 10:16 AM by  kurtl@logicpd.com
PC Card CE1 and CE2 signals
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tony
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13 Oct 2005 08:29 AM
    For my design, I need to use the PC Card CE1 and CE2 signals that aren't brought off the card. I think I could use the decoded ones from the CPLD but the PXA270-10 IO controller specification doesn't give any details as to their use. Can you furnish a timing diagram for PCC_nCExy signals?
    kurtl@logicpd.com
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    13 Oct 2005 10:11 AM
    tony,
    The CPLD uses the state of the GPIO79 (PCC_SLOT_SELECT_A_nB) signal to demux the CE1/CE2 signals to two seperate sets of outputs, one pair for each external PCMCIA slot. If GPIO79 is high and CE1/CE2 from the CPU are asserted, the external MFP20 - PCC_nCE1A and MFP22 - PCC_nCE2A are asserted. If GPIO79 is low and CE1/CE2 from the CPU are asserted, the external PCC_nCE1B and PCC_nCE2B signals are asserted. The logic in the CPLD implements two OR gates and an inverter gate. The result should be max of 10nS time shift in the CE1/CE2 outputs.

    Let us know if you need more assistance.
    tony
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    13 Oct 2005 10:14 AM
    Great! That is what I expected, but it wasn't really described in the spec.

    Thanks!
    kurtl@logicpd.com
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    13 Oct 2005 10:16 AM
    I will get our Apps team to update that doc. Thanks for pointing out the holes!
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