void codec_write(uint16 RegTarget, uint16 Command)
{
uint16 i,tmp;

MCF_QSPI_QAR = 0x20; //Command RAM
MCF_QSPI_QDR = 0x07300;

MCF_QSPI_QIR |= MCF_QSPI_QIR_SPIF; // Clear interrupts
MCF_QSPI_QAR = 0x00;
tmp = (RegTarget << 8) | Command;

MCF_QSPI_QDR = tmp;
MCF_QSPI_QDLYR |= MCF_QSPI_QDLYR_SPE;
i=0x00;
while(i != MCF_QSPI_QIR_SPIF)
{i= MCF_QSPI_QIR & MCF_QSPI_QIR_SPIF;}
};

void data_write()
{
int i,j;



MCF_SSI_CR |= MCF_SSI_CR_TE;

for(i=0;i<1000;i++)
{



MCF_SSI_TX0 = 0xFFFF;
MCF_SSI_TX1 = 0xFFFF;
for (i= 0; i < 1000; i++)
{asm(nop);} //DES}

MCF_SSI_TX0 = 0x0000;
MCF_SSI_TX1 = 0x0000;
}

MCF_SSI_CR &= 0xFFFFFFFD;
};


vuint32 audioInit(void)
{
vuint16 temp16;
vuint32 index;

/********************************/
/* Setup the SPI - control link */
/********************************/
/* QSPI does not operate in slave mode. Set to master. */
temp16 = MCF_QSPI_QMR_MSTR |
MCF_QSPI_QMR_BITS(0x000); // 16 bit xfers

temp16 |= MCF_QSPI_QMR_BAUD(133);
MCF_QSPI_QMR = temp16;

temp16 = MCF_QSPI_QIR_WCEF |
MCF_QSPI_QIR_SPIFE |
MCF_QSPI_QIR_ABRT |
MCF_QSPI_QIR_SPIF; // Clear interrupts
MCF_QSPI_QIR = temp16;

MCF_QSPI_QWR |= MCF_QSPI_QWR_CSIV; //CS return to Hi when inactive

/* Enable the QSPI pins */


MCF_GPIO_PAR_QSPI = ( 0
| MCF_GPIO_PAR_QSPI_PAR_SCK(3)
| MCF_GPIO_PAR_QSPI_PAR_DOUT(3)
| MCF_GPIO_PAR_QSPI_PAR_DIN(3)
| MCF_GPIO_PAR_QSPI_PAR_PCS0(3)
| MCF_GPIO_PAR_QSPI_PAR_PCS1(3)
| MCF_GPIO_PAR_QSPI_PAR_PCS2(3)
);

MCF_QSPI_QDLYR |= 0x01000;


/********************************/
/* Setup the I2S - data link */
/********************************/
/* Enable SSI clock in CCM */

//IRQ1 f?r externe SSICLK schalten
MCF_GPIO_PAR_IRQ |= MCF_GPIO_PAR_IRQ_PAR_IRQ1(0x01);

//MCF_CCM_CDR = MCF_CCM_CDR_SSIDIV(2); // DES changed from 40 to 4 = 12MHz MCLK
// No longer necessary - TI320 directly connected to 10MHz quartz

MCF_SSI_CR =
MCF_SSI_CR_I2S(1) | // Set I2S master mode
MCF_SSI_CR_MCE | // Set clock out on SSI_MCLK pin
MCF_SSI_CR_SYN | // Enable synchronous mode
MCF_SSI_CR_TCH; // Enable two channel mode

MCF_SSI_TCR =
MCF_SSI_TCR_TFEN0 | // TX FIFO 1 enabled
MCF_SSI_TCR_TFEN1 | // TX FIFO 0 enabled
MCF_SSI_TCR_TFDIR | // internally generated frame sync
MCF_SSI_TCR_TXDIR | // internally generated bit clock
MCF_SSI_TCR_TSCKP ; // Clock polarity: 0=clk data on rising edge; 1=clk data on falling edge

MCF_SSI_CCR = MCF_SSI_CCR_WL(7) | // 16 bit word length
MCF_SSI_CCR_DIV2 |
MCF_SSI_CCR_DC(1) | // Frame rate divider - DES DC=1 really mean two words per frame
MCF_SSI_CCR_PM(15); // using equations in section 24.4.2.2 in MCF5329RM.pdf

MCF_SSI_TMASK = MCF_SSI_TMASK_SSI_TMASK(0xfffffffc); //DES Transmit only on time slots 1&2
MCF_SSI_IER = 0; //DES clear/disable interrupts and DMA

MCF_SSI_CR |= MCF_SSI_CR_SSI_EN; //Enable SSI module
/* Enable the SSI pins */
MCF_GPIO_PAR_SSI = ( 0
| MCF_GPIO_PAR_SSI_PAR_MCLK
| MCF_GPIO_PAR_SSI_PAR_TXD(3)
| MCF_GPIO_PAR_SSI_PAR_RXD(3)
| MCF_GPIO_PAR_SSI_PAR_FS(3)
| MCF_GPIO_PAR_SSI_PAR_BCLK(3) );

codec_write(REG_RR, RR_RESET); //reset. do it several time to make sure.
codec_write(REG_RR, RR_RESET);
codec_write(REG_RR, RR_RESET);
codec_write(REG_RR, RR_RESET);
codec_write(REG_RR, RR_RESET);
codec_write(REG_RR, RR_RESET);
for (index = 0; index < 1000; index++) //wait
{
asm(nop); //DES
}


codec_write(REG_PC, (0 )); // Turn on everything
codec_write(REG_DAIF, (0 | DAIF_FOR_I2S )); // Slave, I2S
codec_write(REG_DAP, 0x000); // DES: was 0x000 Set A path...As long as DACM 0 I hear audio
codec_write(REG_SRC, 0x048); // Set sample rate Guess for now, activate clockOut divider for testing functionality
codec_write(REG_AAP, 0x01A); //... , active bypass for testing
codec_write(REG_DIA, DIA_ACT ); // Activate Dig IF
codec_write(REG_RHV, 0x00FF );
codec_write(REG_LHV, 0x00FF );
codec_write(REG_RLIV, 0x001F );
codec_write(REG_LLIV, 0x001F );


return 0;
} /* end init() */