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Last Post 25 Aug 2010 05:29 PM by  tom.evans@motec.com.au
Performance
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aaronjstewart@gmail.com
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10 Mar 2006 12:52 PM
    I noticed that the hardware documentation states that the 5329 evaluation boards runs internally at 240 Mhz. after power-on-reset. This is noted on pages 8 and 9 of the MCF-5329-10 Hardware Specification (Logic PN 1004028). Using the LogicLoader monitor, I looked at the Chip Configuration Register (CCR at 0Xfc0a0004) and a value of 0x0009 was returned. Bit 1(PLL MODE) = 0 indicates that the processor PLL derived clock is running at 180 instead of 240 Mhz.

    First, is this true? If so, how can I achieve the maximum value of 240 Mhz. or was this a design compromise? If the processor clock can be changed to 240 MHz, can this be programmed or must a hardware patch to the CCB be performed?

    This unfolded when I applied a VAX 2.1 Drhystone benchmark and I only obtained 40 dhrystones with video device closed and about 25 dhrystones with video device opened. This performance is much less than the Freescale advertised value of 211 dhrystones. Through this exercise, I was hoping for a value of about 100 dhrystones.

    Any help in moving the clock to 240 Mhz. is appreciated.
    kurtl@logicpd.com
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    10 Mar 2006 01:28 PM
    Hi,
    CCR reflects RCON pin states which set the reset time default operation of the chip. Once the chip is running, you can go into LIMP mode, then change the CPU clock speed. The true operating frequency can only be found by reading back the PFDR and CPUDIV register values. Logic Loader sets these to 0x78 and 0x2 which results in a internal operating frequency of 240Mhz. (freq = 16Mhz x (PFDR)/(4xCPUDIV))

    The user manual re-iterates this information:
    "9.4.2 PLL Mode Selection
    The initial device operating frequency is determined during reset configuration by the D1 pin. The default
    configuration with a 16 MHz input clock is 180 MHz for the core and 60 MHz for the internal bus. The
    user may choose toincrease these frequencies (240 MHz and 80 MHz) by either placing the device in limp
    mode and reconfiguring the appropriate PLL registers, or asserting D1 during reset configuration."

    Are you executing the Drhystone test through Lolo or some other boot loader? Does it operate out of external DDR ram or internal SRAM? These things will all affect performance calculations. Depending your implementation of the test, it could justify the slower speeds than what Freescale advertises. You might also want to get a hold of Freescale and figure out how they implemented their test before you can compare the benchmarks.
    -Kurt
    SimonS
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    30 Oct 2007 05:19 AM
    I've been evaluating the 5329 via the Zoom EVB and have obtained similar results. I haven't been able to get any reason from Freescale other than the suggestion that I was running from Flash not SDRAM and that the cache must have been disabled which was not the case in either instance. Were you able to improve performance above this level, for example by adjusting the SDRAM interface or cache settings? For a very simple loop I would have expected all the code to run from the cache but this doesn't appear to be the case.
    Fabio
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    20 Dec 2007 09:38 AM
    I was quite disappointed to experience that the LogicPD board was not running at 240MHz as specified in the board description. I also had a look at the Freescale doc to find out how to configure the PLL by software, but I was not able to set LIMP mode and and the registers as described. The system crashes. Where is the program executing when you enter LIMP mode? Do you have a software example on how to configure the PLL? Thank you.
    kurtl@logicpd.com
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    20 Dec 2007 12:22 PM
    Fabio,
    Please read my post from above. At reset the board runs at 160Mhz. The logic software (Lolo) sets the clocks to run at 240Mhz and 80Mhz per the specification.

    Good luck with your application.
    -K
    Fabio
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    21 Dec 2007 12:52 AM
    Hi,
    Unfortunately I cannot run LoLo when developing my application with an IDE like GH or Codewarrior. I supposed the hardware did the job as stated in your specification. This is not the case (see D1 pin). So how to set the 240MHz in software now?
    Thank you.
    tom.evans@motec.com.au
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    25 Aug 2010 05:29 PM
    Something like this in your low level startup code. This is lifted from one of the Freescale samples.

    /* NOTE! This clock configuration code should NOT be executed from SDRAM */

    /* Enter limp mode, weak SSI pullups, USB from PLL/4 for 240MHz */
    move.l #MCF_CCM_MISCCR, a0
    move.w #0x10F3,(a0)

    /* Configure PLL settings for 240Mhz */
    move.l #MCF_PLL_PODR, a0
    move.b #0x26,(a0) /* CPUDIV = 2, BUSDIV = 6 */

    move.l #MCF_PLL_PFDR, a0
    move.b #0x78,(a0) /* 16MHz * 0x78 / 8 = 240MHz */

    move.l #MCF_PLL_PLLCR, a0
    move.b #0x00,(a0) /* DITHEN = 0 Dithering Disabled */

    move.l #MCF_PLL_PMDR, a0
    move.b #0x00,(a0) /* Dither Modulation Divider */

    /* Exit limp mode, weak SSI pullups, USB from PLL/4 for 240MHz */
    move.l #MCF_CCM_MISCCR, a0
    move.w #0x00F3,(a0)

    222:
    /* Wait for PLL lock */
    move.w MCF_CCM_MISCCR, d0
    btst #13, d0
    beqs 222b

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