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Last Post 17 May 2007 10:17 AM by Vincent

5484Lite system speed

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dawdyka

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18 Sep 2006 02:07 PM
I've been evaluating the 5484 Fire Engine module for potential use and the only way I can get close to the 200 MHz performance is to have the code and instruction caches enabled (I have code and data both in SDRAM, but I am using 16M blocks for each and using the ACRx registers to differentiate between the two), branch cache enabled, stack in internal SRAM, and the code in internal SRAM. If the code is running in SDRAM, performance is closer to 50 MHz. As far as I can tell, all registers are set to have everything running at the 200 MHz (100 MHz for the bus) speed. Is the performance hit due to the address and data lines being muxed on the module? What kind of performance should I be seeing for code executed from SDRAM?

peter.barada@logicpd.com

New Member
Posts:72

18 Sep 2006 03:20 PM
When the code is in SDRAM, and runs at ~ 50Mhz, is that with the caches enabled? Do you lock any of the ways, or let the cache manage itself? Is the MMU turned on? I wouldn't think the hit is due to a muxed address on the SOM since the SDRAM pins are separate from the flexbus.

dawdyka

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19 Sep 2006 08:46 AM
When the code is in SDRAM and running at ~50 MHz, that is with the caches enabled. I am letting the cache manage itself. The MMU is not turned on. I'm working from the example applications provided with for the M548xEVB LITE, and they do not address MMU functionality. The Freescale MMU documentation doesn't appear to be too straightforward in describing its use, and doesn't provide any examples in how to set it up. The only difference between the SRAM and SDRAM setups is where the code is located.

peter.barada@logicpd.com

New Member
Posts:72

19 Sep 2006 09:05 AM
Can you send me your test app so I can look it over and see if anything jumps out (setup, alignment, register settings, etc)?

dawdyka

New Member
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22 Sep 2006 07:40 AM
I did send you the init files from my test setup. If you didn't get them, please let me know. The processor selection is holding up the project at the moment, so a prompt reply would be appreciated.

Vincent

New Member
Posts:

11 May 2007 08:05 AM
Hi, I am in the same situation as dawdyka: I tried some benchmarks in a code executed from SDRAM with caches enabled and the execution times seem to be very long for a 200MHz core. Have you found an explanation (and a solution) ? Thanks, Vincent.

dawdyka

New Member
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11 May 2007 08:41 AM
I didn't ever hear back from them. I ended up choosing another Coldfire processor that had reasonable measured performance.

Vincent

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17 May 2007 10:17 AM
Hello, Thanks for your answer. I found on the freescale forum others peoples complaining about the same problem. It seems that there is a bug on the interface between the coldfire bus and the XL bus. I think I will be obliged to choose another processor too. Have you any advice to choose a new coldfire processor to replace this one ? Kind regards. Vincent.

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