MIPS with DDR RAM and Coldfire MFC5485

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Last Post 27 Oct 2005 12:57 AM by lucien.perrin

MIPS with DDR RAM and Coldfire MFC5485

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aaronjstewart@gmail.com

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21 Oct 2005 11:13 AM
With the DDRRAM and the Coldfire MCF5485 embedded in the M5485EVB development board, How many MIPS can be expected with code executed from the DDR (CLKIN = 50 MHz CACHE disabled)?

Anonymous
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21 Oct 2005 11:24 AM
Hello, You'll want to refer Section 3.7 of the MCF5455 reference manual entitled "Instruction Execution Timing". This section should have the information that you need to make your calculations. Thank You,

lucien.perrin

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27 Oct 2005 12:57 AM
Posted By aaronlpd on 21 Oct 2005 11:24 AM Hello, You''ll want to refer Section 3.7 of the MCF5455 reference manual entitled "Instruction Execution Timing". This section should have the information that you need to make your calculations. Thank You, The section 3.7 gives the number of cycle by instruction when the instruction is in the cach. My question is around the time to fetch instruction in the DDR RAM and to execute it.

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Forums Freescale / NXP SOMs and Development Kits M54xx EVB ColdFire Development Kit