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Last Post 07 Aug 2007 11:09 AM by  lwalkera
TFT panel timing setup
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steve
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06 Aug 2007 07:41 AM
    I'm adjusting the LCD timing params for a new TFT panel. I have HOR & VER timing dialed in pretty well (looks great), but cannot quite get the pixel clock width & period exactly where I want. I'm using the iMX DI & SDC registers in the 0x53fc0xx range. The LPD signal I want to tune is LCD_CLK: J1[171], iMX31[N21].

    Can anyone give me a tip in the iMX register that defines the LCD pixel clock period and width?

    Thanks for any tips?
    lwalkera
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    07 Aug 2007 11:09 AM
    Try looking at chapter 44 in the iMX31 reference manual. Pages from 44-199 on seem to describe the registers involved in what you're doing.
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