I am currently running McBSP2 to interface to an ADC using the SRG to generate the clock and frame sync and receive into DR. All signals look to have appropriate amplitudes and timing except for the frame sync. Frame sync is ~.9V half of what I expect (1.8V). 

After reviewing all of the SOM and EVM board schematics it looks like there are no connections to the McBSP2 module except to the TPS65950 power module. The SOM schematic specifies that if there are any codecs or external mcbsp modules to set the VIF_TRI_EN and the AIF_TRI_EN bits in the TPS65950 registers to make high Z.

I set the registers using the i2cset method I found in another post from linux command prompt and then initialize my bare metal code. Frame sync amplitude was still low. Then verified that registers where still set to ensure that they were not reinitialized during the running of the bare metal code.

I have been able to get good data from the ADC but only by driving the whole 1.8V but to a higher level ~3.3V which seems dangerous from the datasheets absolute maximum rated range. I have multiple SOMs and verified same functionailty with all units (especially those units not driven to the higher voltage level).

Any sugggestions? I am currently at a loss and am considering a hardware fix but would rather not.