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Last Post 30 Jul 2014 08:39 AM by  Adam Ford
L138/AM1808 Processor Speeds
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Adam Ford



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Posts:754
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--
30 Jul 2014 08:27 AM

     Summary:

    To run at faster speeds, RVDD and CVDD need to be higher than 1.2V.  Since these are not sharing the same supply voltage,
    we need to patch da850.c to adjust both DCDC3 and LDO2 properly.  The instructions below detail how to apply the patch, set the u-boot parameters and confirm the new speeds are available.

     To Apply Patch:

    1.  Builid Kernel and confirm it works without errors.
    2.  Download da850-speed.patch
    3.  cd AM1808_OMAP-L138
    4.  patch -p1 < (path to patch)/da850-speed.patch
    5.  Build kernel (no need to make 'clean' as it will only add more time)
    6.  Install the updated kernel as usual and boot into u-boot

     

    The DA850 and 1808 EVM allows the user to specify the maximum cpu clock allowed by the silicon, in Hz, via an environment variable "maxcpuclk".

    The maximum clock rate allowed depends on the silicon populated on the EVM.

    Please make sure you understand the restrictions placed on this clock in the device specific datasheet before setting up this variable.

    This information is passed to the Linux kernel using the ATAG_REVISION atag. If "maxcpuclk" is not defined, the configuration CONFIG_DA850_EVM_MAX_CPU_CLK is used to obtain this information.


    To set 'maxcpuclk':

    U-Boot > setenv maxcpuclk 456000000
    U-Boot > saveenv
    U-Boot > boot

    To Check Available Speeds:

    root@arago: cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
    456000 408000 372000 300000 200000 96000

    (bolded speeds are only available after the patch and u-boot parameters are applied)

     


    Adam Ford



    Advanced Member


    Posts:754
    Advanced Member


    --
    30 Jul 2014 08:36 AM

    The system in intentionally undervolted a bit due to all the shared components.  Running them all at 1.3V would increase power consumption.

     The following shows the actual measured voltages following a 30 minute stress test at -40C and +85C

    == Set speed and test voltages @ -40C


    root@arago:~# echo 456000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed                                                                               
    root@arago:~# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq
    456000                                                                          
    root@arago:~# cat /sys/class/regulator/regulator.5/microvolts
    1275000                                                                         
    root@arago:~# cat /sys/class/regulator/regulator.3/microvolts
    1275000                                                                         
    root@arago:~# stress --cpu 2 --io 1 --vm 1 --vm-bytes 5M --timeout 1800s --verbose > output-40C

    Measured voltages: 1.271,1.277




    == Set speed and test voltages @ 85C

    root@arago:~# echo 456000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed                                                                               
    root@arago:~# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq
    456000                                                                          
    root@arago:~# cat /sys/class/regulator/regulator.5/microvolts
    1275000                                                                         
    root@arago:~# cat /sys/class/regulator/regulator.3/microvolts
    1275000                                                                         
    root@arago:~# stress --cpu 2 --io 1 --vm 1 --vm-bytes 5M --timeout 1800s --verbose > output85C

    Measured voltages:1.271, 1.279

    Adam Ford



    Advanced Member


    Posts:754
    Advanced Member


    --
    30 Jul 2014 08:39 AM
    --- da850.c    2014-07-15 15:03:31.337386881 -0500
    +++ AM1808_OMAP-L138/Kernel/linux-03.21.00.04/arch/arm/mach-davinci/da850.c    2014-07-14 14:36:52.587282423 -0500
    @@ -1062,8 +1062,8 @@
         .prediv        = 1,
         .mult        = 19,
         .postdiv    = 1,
    -    .cvdd_min    = 1300000,
    -    .cvdd_max    = 1350000,
    +    .cvdd_min    = 1275000,
    +    .cvdd_max    = 1300000,
     };
     
     static const struct da850_opp da850_opp_408 = {
    @@ -1071,8 +1071,8 @@
         .prediv        = 1,
         .mult        = 17,
         .postdiv    = 1,
    -    .cvdd_min    = 1300000,
    -    .cvdd_max    = 1350000,
    +    .cvdd_min    = 1275000,
    +    .cvdd_max    = 1300000,
     };
     
     static const struct da850_opp da850_opp_372 = {
    @@ -1081,7 +1081,7 @@
         .mult        = 31,
         .postdiv    = 1,
         .cvdd_min    = 1200000,
    -    .cvdd_max    = 1320000,
    +    .cvdd_max    = 1300000,
     };
     
     static const struct da850_opp da850_opp_300 = {
    @@ -1090,7 +1090,7 @@
         .mult        = 25,
         .postdiv    = 2,
         .cvdd_min    = 1200000,
    -    .cvdd_max    = 1320000,
    +    .cvdd_max    = 1300000,
     };
     
     static const struct da850_opp da850_opp_200 = {
    @@ -1144,28 +1144,38 @@
     };
     
     #ifdef CONFIG_REGULATOR
    -static struct regulator *cvdd;
    +static struct regulator *cvdd;    // core vdd
    +static struct regulator *rvdd;  // RAM vdd
    +
     
     static int da850_set_voltage(unsigned int index)
     {
         struct da850_opp *opp;
     
    -    if (!cvdd)
    +    if (!cvdd || !rvdd)
             return -ENODEV;
     
         opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
     
    +    regulator_set_voltage(rvdd, opp->cvdd_min, opp->cvdd_max);
         return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
     }
     
     static int da850_regulator_init(void)
     {
         cvdd = regulator_get(NULL, "cvdd");
    +    rvdd = regulator_get(NULL, "vddarnwa1");
         if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
                         " voltage scaling unsupported\n")) {
             return PTR_ERR(cvdd);
         }
     
    +    if (WARN(IS_ERR(rvdd), "Unable to obtain voltage regulator for RVDD;"
    +                                        " voltage scaling unsupported\n")) {
    +                return PTR_ERR(rvdd);
    +        }
    +
    +
         return 0;
     }
     #endif
    @@ -1626,4 +1636,3 @@
         v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
         __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
     }
    -
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