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Last Post 27 Oct 2005 10:33 AM by
Exclusive chip select signal for user memory mapped devices
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New Member

New Member

25 Oct 2005 10:40 AM
    Hi everyone,

    I am facing the problem to attach a memory mapped device our company developed to the Sharp Zoom SDK evaluation board. I got two

    different card engines (LH79520 and LH79524) and the board. Since I need an exclusive chip select signal and there is an open

    memory block that is free for utilization by the user I am wondering if there is a cs signal that comes out of the CPLD when I

    access these addresses (referenced to in the io controller spec).
    That is 0x5700 0000 – 0x57FF FFFF for the LH79520 card engine and 0x4D00 0000 – 0x4FFF FFFF for the LH79524 card engine. There is

    a reference to a signal in the io controler specification of the LH79524 card engine but not in the io controler specification of

    the LH79520.
    The spec of the io controler specification of the LH79520 says there's a chip select signal -> FAST_nCS but I can't find this

    signal whether in the schematics nor anywhere. There's only one signal named similar FAST_nMCS but I think it's not the right one

    because I couldn't see the pin level toggeling when I attach a scope to the specified pin.
    I am not sure if there's a special chip select at all and I have to build an own decoder for the chip select or if there is a chip

    select signal I can use for the user memory area?
    Any help appreciated...thanks in advance!


    New Member

    New Member

    25 Oct 2005 11:04 AM
    On the LH79524, external FAST_nMCS (FAST_nCS is the same signal, the M indicates its a buffered signal) is asserted when chip select 3 is low and A23 is high. It can be found as an output from the card engine on J1C pin 6.

    On the LH79520, external FAST_nMCS is asserted when uP_nCS5 (chip select 5 on the CPU) is asserted. You should be able to use this memory window for your device: 0x53000000 – 0x53FFFFFF

    FAST_nMCS can be found on the SDK on connector J17 pin 7.


    New Member

    New Member

    27 Oct 2005 04:13 AM
    Thanks for your fast reply! I have tried several things but they didn't solve my problem.

    My intention was to find a chip select pin I can use for the chip select of my external memory mapped device.

    So writing/reading in a defined address range should make a chip select pin toggling.

    I've chosen the fast peripherals static memory block, to be more precisely the user range from 0x5700 0000 – 0x57FF FFFF.
    When I access any address in this address range there should be at least the chip select 5 toggling, shouldn't it?
    If I understood right the CPLD decodes the chip select 5 and some address wires to a chip select for the user specific static memory

    area and toggles the FAST_nMCS signal at J17 pin 7 when those addresses are accessed.

    On the LH79520 card engine I tried the following:

    - disabling the cache by typing 'cache-off'
    - loading a little assembler program that:
    * disables the mmu
    * disables alignment faults
    * disables cache
    * disables buffered writing

    * the program loops endless and writes 0xFFFFFFFF to address 0x57000000

    * I would expect the chip select 5 signal to toggle

    Probing at pin 7 on J17 at the SDK doesn't show anything on my scope. Address pins and data pins are toggling but not any of the chip

    selects. Any other ideas what I made wrong?

    I tried other adresses (slow peripherals, probed other chip selects) for writing, too but didn't lead to success!

    One remark:
    You mentioned that the memory address range 0x53000000 – 0x53FFFFFF is associated with chip select 5 but in the io controller spec

    (12/31/2003 rev. D) it is said to be 0x54000000 - 0x57FFFFFF.
    Is there any change in the spec I didn't notice?

    Thanks for any help !


    New Member

    New Member

    27 Oct 2005 10:33 AM
    Do you have PH4 defined as nCS5 in the MemMux register? Without that, the signal will only assert when used as a GPIO. To use with a memory window it must be defined as nCS5.

    Also, regarding the memory regions, you are correct about the addressing. 0x53000000-0x53ffffff is for the SLOW_nCS. 0x5700000-0x57ffffff is for nCS5.
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