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Last Post 22 Aug 2004 06:39 AM by  mike tesch
I/O controller headaches
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gweile@syner-seis.com
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07 Jul 2004 04:35 PM
    Would anyone know the reason why when I peek and poke at the card engines control register at 0x54200000 under LOLO, I/m not able to clear the LAN power enable bit...

    When I read back the registers value, I also see that bit 1 is sometimes set (no documentation I've seen refers to this bit as being of any use)...

    I've only been able to download logics P/N: 70000015 I/O controller spec sheet (next to useless), and would like to know where I can get my hands on some detailed timing data, bit descriptions, blah, blah, blah...

    The Macgraigor Jtag interface I'm using seems to properly toggle bit 0 in the card engine controller... So it could be that LOLO is clearing this bit on it's own and sometimes (for undocumented reasons) periodically sets bit 1

    Pretty weird, huh...
    mike tesch
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    22 Aug 2004 06:39 AM
    Could you post the exact commands you're using to do this? The controller is only a 16-bit wide device (i.e. it decodes only enough address bits to be 16 bits wide) so if you do a 32-bit access at its address, you are actually hitting (r/w) the reg twice. Dont know if that's the problem, but it's a common one.
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