Technical Discussion Group Forum

This forum is provided for user discussion. While Beacon EmbeddedWorks support staff and engineers participate, Beacon EmbeddedWorks does not guarantee the accuracy of all information within in the Technical Discussion Group (TDG).

The "Articles" forums provide brief Articles written by Beacon EmbeddedWorks engineers that address the most frequently asked technical questions.

To receive email notifications when updates are posted for a Beacon EmbeddedWorks product download, please subscribe to the TDG Forum of interest.

TDG Forum

PrevPrev Go to previous topic
NextNext Go to next topic
Last Post 11 May 2006 04:06 PM by  Anonymous
vic/interrupt problems
 1 Replies
You are not authorized to post a reply.
Author Messages
Robert Lepage
New Member
New Member

11 May 2006 12:31 PM
    Hi all,

    I am trying to get uC/OS-II running on an LH75401 SDK, and am having trouble generating a simple interrupt through the VIC. I have RAM relocated to address 0, an instruction set in the IRQ vector (18H) to load the address of the ISR entry, and an ISR that reads from the vic vector address, and the vic setup to pass an interrupt from timer 0.

    I am trying to test this by raising the timer 0 interrupt using the vic software interrupt register. I can step through my code (Signum emulator), watch the initialization, manually clear the I bit in CPSR, and then execute the line to raise the timer 0 interrupt. I then expect to see the code pass through the IRQ vector, and to the ISR. This does not happen; it looks like the interrupt is not seen.

    Any help or comments on my above described init/test sequence, examples of setting up the vic, or an existing port of uC/OS-II to the LH75401 would be greatly appreciated.



    11 May 2006 04:06 PM
    I would check the example code located here.
    You will need to get yourself a login.
    You are not authorized to post a reply.