The diagram on our schematics is an error and doesn't correctly represent the CPLD implementation.
Revsion 3.2 of the CPLD code OR's nCS6 with nRD and nWE0 signal to create NAND_nRE and NAND_nWE.

PC6 is used in the CPLD only to prevent other CPLD interfaces from causing bus contention when nCS6 is asserted for NAND operations.

The PC6 signal is used as the chip select by the boot ROM in Sharp implementations. The reason they use PC6 instead of nCS6 is because most standard NAND devices require the nCE signal be asserted for a long time during NAND address pointer changes inside the NAND device. If nCE is de-asserted during this time the NAND device goes to low power mode and cancels the address change transaction. If Sharp used nCS6 to drive nCE directly bus contention would occur during SDRAM refresh cycles as well as slow down the entire operation of all external memory bus accesses when the NAND address pointer would change. By using PC6 they can keep the nCE low on the NAND chip and use the nCS6 area with the OR gates to read and write to the NAND chip when necessary without causing bus contention. LogicPD uses the nCS6 area for memory mapped registers in the CPLD and the NAND chip.

Sorry for the confusion.
-Kurt

Thanks for clarification. Because we are designing a NAND Flash boot device, we will use nCS6 with nWE and nOE to drive nWE and nRE respectively in NAND Flash device, and PC6 as nCE in NAND Flash device as Sharp recommends in their manuals.
...now the only problem is writing a NAND Flash capable bootloader

Kindest regards,
Gianluca

Hi Gianluca,

The source code for LogicLoader is available for purchase through product sales if you'd like a head start on developing your bootloader. If you're interested in pursuing this path you can reach sales at:

product.sales@logicpd.com

Please post back here if you have further questions.

Thanks,