Ben,
check out the IO Controller Spec. document for the LH7A400 and verify you have the GPACT bit in the expected position.

This bit tells the system CPLD how to deal with the PCMCIA control signals. If it is in PCMCIA mode, it does incorporate the PCMCIA signals into the buffer control equations and could knock over the SDRAM or other external memory if the PCMCIA card enable signals are set up as GPIO.

My bet is that you should leave GPACT a '1' if you disable the write to PCMCIACON.

Hans

Hi hansr,

Thanks for your reply! However, I found that default value of GPACT is 0. And both of bs_7400_dbg.elf and apex do not access this register.

Ben,
set GPACT to a '1'.

It has to be a '1' if you EITHER use the PCMCIA signals as GPIO OR if you don't enable the PCMCIA interface. If it is a '0' (default state), you must ensure the PCMCIA interface is enabled.

The IOController spec states:
GPACT: GPIO active – this bit enables or disables buffer control based on the PCMCIA slot signals. If this bit is 0, the card engine buffers and PCMCIA CE signals will be controlled via the PCMCIA control signals. If this bit is a 1, the buffer control equations will ignore the PCMCIA signals because the user intends to use them as GPIO and not as PCMCIA control signals.
0 = input PCMCIA control signals to CPLD enabled (GPIO disabled).
1 = input PCMCIA control signals to CPLD disabled (GPIO enabled).

Thanks,
Hans

Posted By hansr on 21 Feb 2005 6:53 PM
Ben,
set GPACT to a ''1''.

It has to be a ''1'' if you EITHER use the PCMCIA signals as GPIO OR if you don''t enable the PCMCIA interface. If it is a ''0'' (default state), you must ensure the PCMCIA interface is enabled.

The IOController spec states:
GPACT: GPIO active – this bit enables or disables buffer control based on the PCMCIA slot signals. If this bit is 0, the card engine buffers and PCMCIA CE signals will be controlled via the PCMCIA control signals. If this bit is a 1, the buffer control equations will ignore the PCMCIA signals because the user intends to use them as GPIO and not as PCMCIA control signals.
0 = input PCMCIA control signals to CPLD enabled (GPIO disabled).
1 = input PCMCIA control signals to CPLD disabled (GPIO enabled).

Thanks,
Hans

Sorry for my mistake.

hmm. I have tried to set GPACT to 1 by writing 0x2 to address 0x71A00000. However, once I fetch it again, the return value is 0x0. And ofcoz the SDRAM could not be initializated if the write to PCMCIACON has been disabled.

Ben,
what version is your CPLD code, and what code are you using to access the bit (what address, data and access size)?

That bit has been verified to work in version 0x37 and later of CPLD code - it sounds like the write access is not working correctly.

Hans

Posted By hansr on 22 Feb 2005 10:47 AM
Ben,
what version is your CPLD code, and what code are you using to access the bit (what address, data and access size)?

That bit has been verified to work in version 0x37 and later of CPLD code - it sounds like the write access is not working correctly.

Hans

It is 0x34. Not the most updated one. Is it possible to upgrade it?

What revision of Card Engine are you using (on the label on the card engine)?

CPLD update files are posted on the downloads site for the Card Engine. However, RevA LH7A400-10 card engines cannot be upgraded.

Hans

Thanks! I have upgraded the CPLD.