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Last Post 21 Dec 2004 12:44 PM by  tom@cyberiansoftware.com
JTAG: CPLD goes braindead?
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tom@cyberiansoftware.com
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01 Dec 2004 11:13 AM
    I seem to be seeing a situation in which you attach a JTAG to control the ARM CPU and somehow the CPLD becomes dysfunctional. The problem shows up about 90% of the time when using JTAG to connect to the LH7A400-10 board. The CPLD refused to respond to external logic events, it is dead.

    Looking at the schematic, the JTAG pins to the CPLD are connected to the host CPU via the U19 buffer. Are you using the JTAG in lolo to communicate periodically with the CPLD? Is that why the CPLD goes inert when the ARM CPU enters JTAG modes because the CPLD is suddenly caught in an inert (uncompleted JTAG conversation) state?

    BTW, I am in no way, intentionally, attempting to operate the JTAG on the CPLD, only the ARM CPU.
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    21 Dec 2004 12:30 PM
    Lolo does not use the JTAG to communicate with the CPLD. Lolo configures PA2 to an output and sets it high.
    tom@cyberiansoftware.com
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    21 Dec 2004 12:44 PM
    Thanks, I see that, the CPU JTAG is not connected to the CPLD JTAG. The CPU would be running a program to operate the JTAG lines of the CPLD. Since there does not appear to be any information, for low-level operation of the Card Engine, it appeared that some clock / signal line needed to achieve state before the CPLD was operational. e.g. PA2 has to be set HI before the CPLD is operational.

    By low-level operation, I mean such as the instance of seizing control over the Card Engine via a JTAG. Normally, their bolo boot would come up and initialize the system. Without the bolo initialization, what initializations must be performed? i.e. What values must be written into the CPLD to idle it down, or GPIO pin states on the CPU must be set so that the CPLD is not "locked up".

    For example, if you don't disable the PCMCIA within the CPLD and attempt to operated the GPIO ports G of the CPU, this will lockup the CPLD.
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