I am using the OMAP-L138 EVM development kit and trying to evaluate the DAC/ADC feature of the User interface board. From the TI literature SPRUGJ5B, the sampling clock is fixed at 150/(2+upicr.clkdiv +1). The slowest sampling frequency is 4.69 Mhz. Is there any way that I can lower the clock down to may be a 1Mhz ?

Thanks,
Kevin