Thanks, I see that, the CPU JTAG is not connected to the CPLD JTAG. The CPU would be running a program to operate the JTAG lines of the CPLD. Since there does not appear to be any information, for low-level operation of the Card Engine, it appeared that some clock / signal line needed to achieve state before the CPLD was operational. e.g. PA2 has to be set HI before the CPLD is operational.
By low-level operation, I mean such as the instance of seizing control over the Card Engine via a JTAG. Normally, their bolo boot would come up and initialize the system. Without the bolo initialization, what initializations must be performed? i.e. What values must be written into the CPLD to idle it down, or GPIO pin states on the CPU must be set so that the CPLD is not "locked up".
For example, if you don't disable the PCMCIA within the CPLD and attempt to operated the GPIO ports G of the CPU, this will lockup the CPLD.
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