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tony,
The CPLD uses the state of the GPIO79 (PCC_SLOT_SELECT_A_nB) signal to demux the CE1/CE2 signals to two seperate sets of outputs, one pair for each external PCMCIA slot. If GPIO79 is high and CE1/CE2 from the CPU are asserted, the external MFP20 - PCC_nCE1A and MFP22 - PCC_nCE2A are asserted. If GPIO79 is low and CE1/CE2 from the CPU are asserted, the external PCC_nCE1B and PCC_nCE2B signals are asserted. The logic in the CPLD implements two OR gates and an inverter gate. The result should be max of 10nS time shift in the CE1/CE2 outputs.
Let us know if you need more assistance.
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