We have a MCF5475 EVB. We sample 5 GPIO pins (configured for input) but we'd like up to 8 pins available for GPIO input. The problem is, they have to be sampled by the same PPDSDR register. We must sample just 1 register. Sampling 2 registers is not acceptable due to performance issues.

At present we're using the Mini-ITX Case Header on the Logic MCF5475EVB which exposes 5 DSPI pins which can be configured for GPIO input (the other 2 pins in the register are used elsewhere on the board - USB and JTAG/CPLD I think). These are all read via a single read of the PPDSDR_DPSI register.

Unfortunately, some of the GPIO lines aren't configurable for input, only output (and vice versa), and I'm unable to find a clear point in the manuals which explains if particular lines can be GPIO input, output or both.

The following PPDSDR registers are the only ones suitable for investigation:

8 bit
PPDSDR_FBCTL
PPDSDR_FEC0H
PPDSDR_FEC0L
PPDSDR_FEC1H
PPDSDR_FEC1L
PPDSDR_PSC3PSC2
PPDSDR_PSC1PSC0

Does anyone know if the above 8 bit PPDSDR registers can more than 5 lines configured for GPIO *input*?

Thanks

David