; iMX31LiteKit.mac - Startup macro for LogicPD MCiMX31LiteKit board with Freescale i.MX31 processor (ARM1136JF_S)
; Version 1.00 12/11/2007 - Initial version
;

refresh mode disable ; disable display of windows here

if __CPU_STATE__ == "Unknown"
echo off
echo
echo Error: Cannot access the CPU.
echo
echo on
exit
endif

if __CPU_STATE__ == "NoPower"
echo off
echo
echo No power. Power the target up now.
echo
while __CPU_STATE__ == "NoPower"
; Wait for power.
endwhile
echo on
endif

if __CPU_STATE__ == "InReset"
echo off
echo
echo CPU in reset. Waiting for release from reset.
echo
while __CPU_STATE__ == "InReset"
; Waiting for release from reset.
endwhile
echo on
endif

if __CPU_STATE__ == "Running"
; stop CPU
stop
endif


; Load definition of registers for this CPU and/or board
loadreg ARM\iMX31.def ; Processor peripherals

; define memory mapping ...

map all none ; clear an old mapping

map 0x0000_0000 L 16K user rdonly ; Secure ROM
map 0x0040_4000 L 16K user rdonly ; Internal ROM
map 0x1000_0000 L 256M user ; Internal RAM aliasing
map 0x1FFF_C000 L 16K user ; Internal RAM
map 0x3000_0000 0x5FFF_FFFF user device ; Peripherals
map 0x6000_0000 L 128M user rdonly ; ROMPATCH
map 0x6800_0000 L 128M user device ; VIC
map 0x7000_0000 L 256M user device ; IPU (MAX M2)
map 0x8000_0000 L 128M user ; CS0/CS2 DDR SDRAM
map 0x8800_0000 L 128M user ; CS0/CS2 DDR SDRAM (alias)
;map 0x9000_0000 L 128M user ; CSD1 SDRAM/DDR
map 0xA000_0000 L 4M user rdonly ; CS0 Burst FLASH
;map 0xA800_0000 L 128M user rdonly ; CS1 (Flash) 64 Mbyte
;map 0xB000_0000 L 32M user ; CS2 (SRAM)
;map 0xB200_0000 L 32M user ; CS3 (Spare)
map 0xB400_0000 L 32M user device ; PBC registers
map 0xB401_0000 L 32 user device ; CS4 External DUART
map 0xB402_0000 L 64K user device ; CS4 Ethernet Controller
map 0xB403_0000 L 2 user device ; CS4 YMU782B synth
map 0xB400_0000 L 58 user device ; CS4 CPLD & MMIO (for I/O operations only D[15:0] are used)
map 0xB600_0000 L 32M user ; CS5 (spare)
map 0xB600_0000 L 16M user ; CS5 PSRAM
map 0xB800_0000 0xC3FF_FFFF user device ; peripherals

CP15_CONTROL=0x78

gosub InitSystem
gosub DisableWatchdog
gosub FlashProgrammer

; display current mapping
map

refresh mode enable ; enable display of windows here

exit ; Done.

;------------------------------------------
; Subroutines
;------------------------------------------

; DisableWatchdog
:DisableWatchdog [menu] ; Disable watchdog
-refresh mode disable
return
; End of DisableWatchdog

:FlashProgrammer [menu] ; Setup the flash programmer in external RAM at 0x8000_0000
-refresh mode disable
plugin paramset FlashDevice.FlashDevice="CFI 16-bit flash programmer (fits 64K RAM)"
plugin paramset FlashDevice.Options="-ma0x7ff"
plugin paramset FlashDevice.BaseAddress="0xA000_0000"
plugin paramset FlashDevice.RamAddress="0x8000_0000"
return
; End of FlashProgrammer

:TinyFlashProgrammer [menu] ; Setup the flash programmer in 16K internal RAM at 0x1000_0000
-refresh mode disable
plugin paramset FlashDevice.FlashDevice="CFI 16-bit flash programmer (fits 16K RAM)"
plugin paramset FlashDevice.Options="-ma0x7ff"
plugin paramset FlashDevice.BaseAddress="0xA000_0000"
plugin paramset FlashDevice.RamAddress="0x1000_0000"
return
; End of FlashProgrammer

:InitSystem [menu] ; Initialize system
-refresh mode disable

IPU_CONF = 0x040 ; setup IPU
CCMR = 0x074B0B7D ; init CCM
PDR0 = 0xFF871D58 ; 532-133-66.5
MPCTL = 0x0033280C
CSCR0U = 0x0000CF03 ; Start 16 bit NorFlash Initialization on CS0
CSCR0L = 0xa0330D01
CSCR0A = 0x00220800

gosub SetupSDRAM_IO
gosub SetupSDRAM

return
; End of InitSystem

:SetupSDRAM [menu] ; Setup SDRAM
-refresh mode disable
ESDCFG0 = 0x6AC73A ; SDRAM timing
ESDMISC = 0x2 ; Reset
ESDMISC = 0x4 ; Select DDR
pause 1
ESDCTL0 = 0x92100000 ; Precharge command
sd 0x80000F00 = 0x0 ; Precharge all banks
ESDCTL0 = 0xA2100000 ; Autorefresh command
sd 0x80000000 = 0x0 ; Refresh all banks
sd 0x80000000 = 0x0
ESDCTL0 = 0xB2100000 ; Load-mode command
sb 0x80000033 = 0x0 ; Load mode register
sb 0x81000000 = 0x0
; ESDCTL0 = 0x82226C80 ; Load-mode command
ESDCTL0 = 0x82226080 ; Load-mode command
ESDMISC = 0xC
return
; End of SetupSDRAM

:SetupSDRAM_IO [menu] ; Setup SDRAM I/O pads
-refresh mode disable
; Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
; in SW_PAD_CTL registers
;
s32 0x43FAC26C = 0x121A8DA0 ; SDCLK - Clear pad bit 12. Reset value 0x121A9DA0
s32 0x43FAC270 = 0x12348521 ; CAS - Clear pad bit 22. Reset value 0x12748521
s32 0x43FAC274 = 0x2A328D23 ; RAS - Clear pad bit 2. Reset value 0x2A328D27
s32 0x43FAC27C = 0x12349CA3 ; CS2 (CSD0) - Clear pad bit 22. Reset value 0x12749CA3
s32 0x43FAC284 = 0x12328DA3 ; DQM3 - Clear pad bit 22. Reset value 0x12728DA3
s32 0x43FAC288 = 0x12348D23 ; DQM2, DQM1, DQM0 - Clear pad bit 2,12,22. Reset value 0x12749D27
s32 0x43FAC28C = 0x12348D23 ; SD31-SD29 - Clear pad bit 2,12,22. Reset value 0x12749D27
s32 0x43FAC290 = 0x12348D23 ; SD28-SD26 - Clear pad bit 2,12,22. Reset value 0x12749D27
s32 0x43FAC294 = 0x12348D23 ; SD25-SD23 - Clear pad bit 2,12,22. Reset value 0x12749D27
s32 0x43FAC298 = 0x12348D23 ; SD22-SD20 - Clear pad bit 2,12,22. Reset value 0x12749D27
s32 0x43FAC29C = 0x12348D23 ; SD19-SD17 - Clear pad bit 2,12,22. Reset value 0x12749D27
s32 0x43FAC2A0 = 0x12348D23 ; SD16-SD14 - Clear pad bit 2,12,22. Reset value 0x12749D27
s32 0x43FAC2A4 = 0x12348D23 ; SD13-SD11 - Clear pad bit 2,12,22. Reset value 0x12749D27
s32 0x43FAC2A8 = 0x12348D23 ; SD10-SD8 - Clear pad bit 2,12,22. Reset value 0x12749D27
s32 0x43FAC2AC = 0x12348D23 ; SD7-SD5 - Clear pad bit 2,12,22. Reset value 0x12749D27
s32 0x43FAC2B0 = 0x12348D23 ; SD4-SD2 - Clear pad bit 2,12,22. Reset value 0x12749D27
s32 0x43FAC2B4 = 0x0A148D23 ; SD1-SD0 - Clear pad bit 2,12. Reset value 0x0A149D27
s32 0x43FAC2B8 = 0x0A328CA1 ; A25-A24 - Clear pad bit 12, 22. Reset value 0x0A729CA1
s32 0x43FAC2BC = 0x0A328CA3 ; A23-A21 - Clear pad bit 2, 12, 22. Reset value 0x0A729CA7
s32 0x43FAC2C0 = 0x0A328CA3 ; A20-A18 - Clear pad bit 2, 12, 22. Reset value 0x0A729CA7
s32 0x43FAC2C4 = 0x0A328CA3 ; A17-A15 - Clear pad bit 2, 12, 22. Reset value 0x0A729CA7
s32 0x43FAC2C8 = 0x0A328CA3 ; A14-A12 - Clear pad bit 2, 12, 22. Reset value 0x0A729CA7
s32 0x43FAC2CC = 0x0A328CA3 ; A11-A10, MA10 - Clear pad bit 2, 12, 22. Reset value 0x0A729CA7
s32 0x43FAC2D0 = 0x0A328CA3 ; A9-A7 - Clear pad bit 2, 12, 22. Reset value 0x0A729CA7
s32 0x43FAC2D4 = 0x0A328CA3 ; A6-A4 - Clear pad bit 2, 12, 22. Reset value 0x0A729CA7
s32 0x43FAC2D8 = 0x0A328CA3 ; A3-A1- Clear pad bit 2, 12, 22. Reset value 0x0A729CA7
s32 0x43FAC2DC = 0x0A0280A3 ; A0 - Clear pad bit 2. Reset value 0x0A0280A7
return
; End of SetupSDRAM


; End of file 'iMX31LiteKit.mac'