I'm adjusting the LCD timing params for a new TFT panel. I have HOR & VER timing dialed in pretty well (looks great), but cannot quite get the pixel clock width & period exactly where I want. I'm using the iMX DI & SDC registers in the 0x53fc0xx range. The LPD signal I want to tune is LCD_CLK: J1[171], iMX31[N21].
Can anyone give me a tip in the iMX register that defines the LCD pixel clock period and width?
Thanks for any tips?
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